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[34.83.12.150]) by smtp.gmail.com with ESMTPSA id b2-20020a639302000000b003808dc4e133sm505007pge.81.2022.03.23.13.13.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 13:13:36 -0700 (PDT) Date: Wed, 23 Mar 2022 13:13:32 -0700 From: Ricardo Koller To: Oliver Upton Cc: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220323_131343_125133_E0F4C3FB X-CRM114-Status: GOOD ( 26.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote: > Hi Reiji, > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > > Add hidden or reserved ID registers, and remaining ID registers, > > which don't require special handling, to id_reg_desc_table. > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > > or reserved registers. Since now id_reg_desc_init() is called even > > for hidden/reserved registers, change it to not do anything for them. > > > > Signed-off-by: Reiji Watanabe > > I think there is a very important detail of the series that probably > should be highlighted. We are only allowing AArch64 feature registers to > be configurable, right? AArch32 feature registers remain visible with > their default values passed through to the guest. If you've already > stated this as a precondition elsewhere then my apologies for the noise. Aren't AArch64 ID regs architecturally mapped to their AArch32 counterparts? They should show the same values. I'm not sure if it's a problem (and if KVM is faithful to that rule), > > I don't know if adding support for this to AArch32 registers is > necessarily the right step forward, either. 32 bit support is working > just fine and IMO its OK to limit new KVM features to AArch64-only so > long as it doesn't break 32 bit support. Marc of course is the authority > on that, though :-) > > If for any reason a guest uses a feature present in the AArch32 feature > register but hidden from the AArch64 register, we could be in a > particularly difficult position. Especially if we enabled traps based on > the AArch64 value and UNDEF the guest. > > One hack we could do is skip trap configuration if AArch32 is visible at > either EL1 or EL0, but that may not be the most elegant solution. > Otherwise, if we are AArch64-only at every EL then the definition of the > AArch32 feature registers is architecturally UNKNOWN, so we can dodge > the problem altogether. What are your thoughts? > > -- > Thanks, > Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel