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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id a3-20020a5ec303000000b006496b4dd21csm378009iok.5.2022.03.23.12.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 12:53:17 -0700 (PDT) Date: Wed, 23 Mar 2022 19:53:14 +0000 From: Oliver Upton To: Reiji Watanabe Cc: Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220311044811.1980336-12-reijiw@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220323_125319_393655_0390538F X-CRM114-Status: GOOD ( 16.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Reiji, On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > Add hidden or reserved ID registers, and remaining ID registers, > which don't require special handling, to id_reg_desc_table. > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > or reserved registers. Since now id_reg_desc_init() is called even > for hidden/reserved registers, change it to not do anything for them. > > Signed-off-by: Reiji Watanabe I think there is a very important detail of the series that probably should be highlighted. We are only allowing AArch64 feature registers to be configurable, right? AArch32 feature registers remain visible with their default values passed through to the guest. If you've already stated this as a precondition elsewhere then my apologies for the noise. I don't know if adding support for this to AArch32 registers is necessarily the right step forward, either. 32 bit support is working just fine and IMO its OK to limit new KVM features to AArch64-only so long as it doesn't break 32 bit support. Marc of course is the authority on that, though :-) If for any reason a guest uses a feature present in the AArch32 feature register but hidden from the AArch64 register, we could be in a particularly difficult position. Especially if we enabled traps based on the AArch64 value and UNDEF the guest. One hack we could do is skip trap configuration if AArch32 is visible at either EL1 or EL0, but that may not be the most elegant solution. Otherwise, if we are AArch64-only at every EL then the definition of the AArch32 feature registers is architecturally UNKNOWN, so we can dodge the problem altogether. What are your thoughts? -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel