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[34.68.225.194]) by smtp.gmail.com with ESMTPSA id k5-20020a6bf705000000b00649a2634725sm470970iog.17.2022.03.23.13.44.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Mar 2022 13:44:29 -0700 (PDT) Date: Wed, 23 Mar 2022 20:44:26 +0000 From: Oliver Upton To: Ricardo Koller Cc: Reiji Watanabe , Marc Zyngier , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Suzuki K Poulose , Paolo Bonzini , Will Deacon , Andrew Jones , Fuad Tabba , Peng Liang , Peter Shier , Jing Zhang , Raghavendra Rao Anata Subject: Re: [PATCH v6 11/25] KVM: arm64: Add remaining ID registers to id_reg_desc_table Message-ID: References: <20220311044811.1980336-1-reijiw@google.com> <20220311044811.1980336-12-reijiw@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220323_134432_903105_CFD19561 X-CRM114-Status: GOOD ( 22.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Mar 23, 2022 at 01:13:32PM -0700, Ricardo Koller wrote: > On Wed, Mar 23, 2022 at 07:53:14PM +0000, Oliver Upton wrote: > > Hi Reiji, > > > > On Thu, Mar 10, 2022 at 08:47:57PM -0800, Reiji Watanabe wrote: > > > Add hidden or reserved ID registers, and remaining ID registers, > > > which don't require special handling, to id_reg_desc_table. > > > Add 'flags' field to id_reg_desc, which is used to indicates hiddden > > > or reserved registers. Since now id_reg_desc_init() is called even > > > for hidden/reserved registers, change it to not do anything for them. > > > > > > Signed-off-by: Reiji Watanabe > > > > I think there is a very important detail of the series that probably > > should be highlighted. We are only allowing AArch64 feature registers to > > be configurable, right? AArch32 feature registers remain visible with > > their default values passed through to the guest. If you've already > > stated this as a precondition elsewhere then my apologies for the noise. > > Aren't AArch64 ID regs architecturally mapped to their AArch32 > counterparts? They should show the same values. I'm not sure if it's a > problem (and if KVM is faithful to that rule), I believe it's a bit more subtle than that. The AArch32 feature registers are architecturally mapped to certain encodings accessible from AArch64. For example, ID_PFR0_EL1 is actually a 64 bit register where bits [31:0] map to the ID_PFR0 AArch32 register. ID_PFR0_EL1 is only accessible from AArch64 with the MRS instruction, and ID_PFR0 is only accessible from AArch32 with the MRC instruction. KVM just so happens to handle both of these reads from the same sys_reg_desc. AFAIK, there does not exist a direct bit mapping between the ID_*_EL1 <-> ID_AA64*_EL1 registers. But hey, could be wrong :) -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel