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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id g8-20020a9d2d88000000b005b238f7551csm462301otb.53.2022.03.31.17.15.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 31 Mar 2022 17:15:30 -0700 (PDT) Received: (nullmailer pid 1762367 invoked by uid 1000); Fri, 01 Apr 2022 00:15:29 -0000 Date: Thu, 31 Mar 2022 19:15:29 -0500 From: Rob Herring To: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= Cc: "Peng Fan (OSS)" , ulf.hansson@linaro.org, krzk+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, wg@grandegger.com, mkl@pengutronix.de, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, qiangqing.zhang@nxp.com, devicetree@vger.kernel.org, Peng Fan , netdev@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-can@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 0/4] dt-bindings: imx: add nvmem property Message-ID: References: <20220324042024.26813-1-peng.fan@oss.nxp.com> <20220324111104.cd7clpkzzedtcrja@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220324111104.cd7clpkzzedtcrja@pengutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220331_171533_446277_AE084C4F X-CRM114-Status: GOOD ( 27.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 24, 2022 at 12:11:04PM +0100, Uwe Kleine-K=F6nig wrote: > Hello, > = > On Thu, Mar 24, 2022 at 12:20:20PM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan > > = > > To i.MX SoC, there are many variants, such as i.MX8M Plus which > > feature 4 A53, GPU, VPU, SDHC, FLEXCAN, FEC, eQOS and etc. > > But i.MX8M Plus has many parts, one part may not have FLEXCAN, > > the other part may not have eQOS or GPU. > > But we use one device tree to support i.MX8MP including its parts, > > then we need update device tree to mark the disabled IP status "disable= d". > > = > > In NXP U-Boot, we hardcoded node path and runtime update device tree > > status in U-Boot according to fuse value. But this method is not > > scalable and need encoding all the node paths that needs check. > > = > > By introducing nvmem property for each node that needs runtime update > > status property accoridng fuse value, we could use one Bootloader > > code piece to support all i.MX SoCs. > > = > > The drawback is we need nvmem property for all the nodes which maybe > > fused out. > = > I'd rather not have that in an official binding as the syntax is > orthogonal to status =3D "..." but the semantic isn't. Also if we want > something like that, I'd rather not want to adapt all bindings, but > would like to see this being generic enough to be described in a single > catch-all binding. > = > I also wonder if it would be nicer to abstract that as something like: > = > / { > fuse-info { > compatible =3D "otp-fuse-info"; > = > flexcan { > devices =3D <&flexcan1>, <&flexcan2>; > nvmem-cells =3D <&flexcan_disabled>; > nvmem-cell-names =3D "disabled"; > }; > = > m7 { > .... > }; > }; > }; > = > as then the driver evaluating this wouldn't need to iterate over the > whole dtb but just over this node. But I'd still keep this private to > the bootloader and not describe it in the generic binding. There's been discussions (under the system DT umbrella mostly) about = bindings for peripheral enable/disable control/status. Most of the time = it is in context of device assignment to secure/non-secure world or = partitions in a system (via a partitioning hypervisor). This feels like the same thing and could use the same binding. But = someone has to take into account all the uses and come up with = something. One off solutions are a NAK. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel