From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A928C433F5 for ; Fri, 1 Apr 2022 17:23:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=F19Z0lZD2E11jGfuY/mF/BEcfSNbLvaV3Qqk/8DfNLs=; b=f0puwedcQfOS0V qlDcZGgViU6SZwbfmkTiafVE4uN1xMZXDVVZjC4uv5DVbT/WML47Q92YObrQfM1YiSnKh+3iSfsBW jPNvndXZa9xDkvd7i/84QSYRU0iQCAgCEJAO5dR3Ai04UY7alIi20yGHMcPhB/tjAgCAkWR2+mhn7 /8/kg1CxIh/+zX1yoKfmh5qcV70qGPOTTorBQ5oG+j162ZoLPfFSMxB8PuuRiw3BByWkFccYZ39SV CrrQGWiSIRVZTQ9wcAsfirTwxWHO9w5VZIqSB37lkBfIeIZtLU1MXrWhSvAssu3LkCG4saOsyhkhG gKegcEazakI7D7rqbF3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1naKyo-006gUh-1e; Fri, 01 Apr 2022 17:22:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1naKyk-006gRP-6r for linux-arm-kernel@lists.infradead.org; Fri, 01 Apr 2022 17:22:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5DB4911FB; Fri, 1 Apr 2022 10:22:26 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.6.144]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 900493F66F; Fri, 1 Apr 2022 10:22:24 -0700 (PDT) Date: Fri, 1 Apr 2022 18:22:14 +0100 From: Mark Rutland To: Jeremy Linton Cc: linux-arm-kernel@lists.infradead.org, gcc@gcc.gnu.org, catalin.marinas@arm.com, will@kernel.org, marcan@marcan.st, maz@kernel.org, linux-kernel@vger.kernel.org, szabolcs.nagy@arm.com, f.fainelli@gmail.com, opendmb@gmail.com Subject: Re: [PATCH] arm64/io: Remind compiler that there is a memory side effect Message-ID: References: <20220401164406.61583-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220401164406.61583-1-jeremy.linton@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220401_102230_378180_7A6F1C86 X-CRM114-Status: GOOD ( 26.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jeremy, Thanks for raising this. On Fri, Apr 01, 2022 at 11:44:06AM -0500, Jeremy Linton wrote: > The relaxed variants of read/write macros are only declared > as `asm volatile()` which forces the compiler to generate the > instruction in the code path as intended. The only problem > is that it doesn't also tell the compiler that there may > be memory side effects. Meaning that if a function is comprised > entirely of relaxed io operations, the compiler may think that > it only has register side effects and doesn't need to be called. As I mentioned on a private mail, I don't think that reasoning above is correct, and I think this is a miscompilation (i.e. a compiler bug). The important thing is that any `asm volatile` may have a side effects generally outside of memory or GPRs, and whether the assembly contains a memory load/store is immaterial. We should not need to add a memory clobber in order to retain the volatile semantic. See: https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Volatile ... and consider the x86 example that reads rdtsc, or an arm64 sequence like: | void do_sysreg_thing(void) | { | unsigned long tmp; | | tmp = read_sysreg(some_reg); | tmp |= SOME_BIT; | write_sysreg(some_reg); | } ... where there's no memory that we should need to hazard against. This patch might workaround the issue, but I don't believe it is a correct fix. > For an example function look at bcmgenet_enable_dma(), before the > relaxed variants were removed. When built with gcc12 the code > contains the asm blocks as expected, but then the function is > never called. So it sounds like this is a regression in GCC 12, which IIUC isn't released yet per: https://gcc.gnu.org/gcc-12/changes.html ... which says: | Note: GCC 12 has not been released yet Surely we can fix it prior to release? Thanks, Mark. > > Signed-off-by: Jeremy Linton > --- > arch/arm64/include/asm/io.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h > index 7fd836bea7eb..3cceda7948a0 100644 > --- a/arch/arm64/include/asm/io.h > +++ b/arch/arm64/include/asm/io.h > @@ -24,25 +24,25 @@ > #define __raw_writeb __raw_writeb > static inline void __raw_writeb(u8 val, volatile void __iomem *addr) > { > - asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); > + asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr) : "memory"); > } > > #define __raw_writew __raw_writew > static inline void __raw_writew(u16 val, volatile void __iomem *addr) > { > - asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); > + asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr) : "memory"); > } > > #define __raw_writel __raw_writel > static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) > { > - asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); > + asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr) : "memory"); > } > > #define __raw_writeq __raw_writeq > static inline void __raw_writeq(u64 val, volatile void __iomem *addr) > { > - asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); > + asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr) : "memory"); > } > > #define __raw_readb __raw_readb > -- > 2.35.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel