From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0775EC433EF for ; Tue, 5 Apr 2022 13:06:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xyC3Fe22/8CClm3fr9FPZcMX4R3MuC6K6aM7ut81SgQ=; b=utVWEFvrMXSlRv noUSEqeMN8Xd+bFha18fBD3+Xf4AEOenLwX9bfsjnMi2lBvjDR2+TK9qSvxtZQv4bnE6H3BO3iMuv Z9A3yGFvyEBJxJS+SvV3Rpa58f0HWFkdpaqksE0gsBIS1gJsxKfqXuktQ4+Ee7lWCTJFBWHdYWcx8 XtZcR6bgQxc/3Pq/wWIBda5MrtnEsVwSPl+0DyCdQMVx61RnWTSuNLJCHC1E5dqdWbwqB0yr6pXCc JaooUmmynycmuBEym8QrXmSWmdLwE1bmgzWbhsRxn9Qe6nqCXfszDibLUSqaOd9bE+12o/GiHYf0v d/OTLCTOTF6/EmoQ3lGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbirr-00133p-Mv; Tue, 05 Apr 2022 13:05:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbird-0012ws-AY for linux-arm-kernel@lists.infradead.org; Tue, 05 Apr 2022 13:04:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 41AECD6E; Tue, 5 Apr 2022 06:04:52 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.8.234]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B8213F5A1; Tue, 5 Apr 2022 06:04:49 -0700 (PDT) Date: Tue, 5 Apr 2022 14:04:45 +0100 From: Mark Rutland To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: linux-arch@vger.kernel.org, gcc@gcc.gnu.org, catalin.marinas@arm.com, will@kernel.org, marcan@marcan.st, maz@kernel.org, szabolcs.nagy@arm.com, f.fainelli@gmail.com, opendmb@gmail.com, Andrew Pinski , Ard Biesheuvel , Peter Zijlstra , x86@kernel.org, andrew.cooper3@citrix.com, Jeremy Linton Subject: Re: GCC 12 miscompilation of volatile asm (was: Re: [PATCH] arm64/io: Remind compiler that there is a memory side effect) Message-ID: References: <20220401164406.61583-1-jeremy.linton@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220405_060453_464707_DE14B405 X-CRM114-Status: GOOD ( 10.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Sorry, I copied the wrong version of the x86_64 assembly as generated by GCC 11.2.0). Updated below. On Tue, Apr 05, 2022 at 01:51:30PM +0100, Mark Rutland wrote: > My x86_64 test case is: > > | unsigned long rdmsr(unsigned long reg) > | { > | unsigned int lo, hi; > | > | asm volatile( > | "rdmsr" > | : "=d" (hi), "=a" (lo) > | : "c" (reg) > | ); > | > | return ((unsigned long)hi << 32) | lo; > | } > | > | void wrmsr(unsigned long reg, unsigned long val) > | { > | unsigned int lo = val; > | unsigned int hi = val >> 32; > | > | asm volatile( > | "wrmsr" > | : > | : "d" (hi), "a" (lo), "c" (reg) > | ); > | } > | > | void msr_rmw_set_bits(unsigned long reg, unsigned long bits) > | { > | unsigned long val; > | > | val = rdmsr(reg); > | val |= bits; > | wrmsr(reg, val); > | } > | > | void func_with_msr_side_effects(unsigned long reg) > | { > | msr_rmw_set_bits(reg, 1UL << 0); > | msr_rmw_set_bits(reg, 1UL << 1); > | msr_rmw_set_bits(reg, 1UL << 2); > | msr_rmw_set_bits(reg, 1UL << 3); > | } > > Per compiler explorer (https://godbolt.org/z/cveff9hq5) GCC trunk currently > compiles this as: > > | msr_rmw_set_bits: > | mov rcx, rdi > | rdmsr > | sal rdx, 32 > | mov eax, eax > | or rax, rsi > | or rax, rdx > | mov rdx, rax > | shr rdx, 32 > | wrmsr > | ret > | func_with_msr_side_effects: > | ret > GCC 11.2 compiles that as: | rdmsr: | mov rcx, rdi | rdmsr | sal rdx, 32 | mov eax, eax | or rax, rdx | ret | wrmsr: | mov rax, rsi | mov rdx, rsi | shr rdx, 32 | mov rcx, rdi | wrmsr | ret | msr_rmw_set_bits: | mov rcx, rdi | rdmsr | sal rdx, 32 | mov eax, eax | or rax, rsi | or rax, rdx | mov rdx, rax | shr rdx, 32 | wrmsr | ret | func_with_msr_side_effects: | push rbx | mov rbx, rdi | mov esi, 1 | call msr_rmw_set_bits | mov esi, 2 | mov rdi, rbx | call msr_rmw_set_bits | mov esi, 4 | mov rdi, rbx | call msr_rmw_set_bits | mov esi, 8 | mov rdi, rbx | call msr_rmw_set_bits | pop rbx | ret Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel