From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AF18DC433F5 for ; Tue, 5 Apr 2022 14:37:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5XbDNYVx/nMi4ToYEC3c0fuu/TiNrfgX+lE3rqIgp5Y=; b=Hei87gVJLFuZ2I /u5ioJec7cIUxt/uC9DQbaNRcJCKl2GsDOEewEJfobBMCZaxssBrmnMNKCb5NKr6Y3vSl8NiyPbXC obTeGZnKbn9CIFJdTrYIH6sHeysGt2SA6OzORdJTFc0cF9/Bxahzpjbqvg1R4nbEa4gba4bBd+Nm7 AMFtiuxjheZkq9OE1oy//ZtSGHsCAu8DfgLuJAmL6YJewU1rdSI0Wx7NgZUw2CKN7UvmQ9bw8eVUk 1CWqlfc/yIsdvrMxDdzCqQnShY2bojz3M1fr9nPEv/J9dj/LyIX6zdXGqIGcDfnG1cPYG1jQpAofT E0O/D/hiJJSjXaOXkI5g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbkIZ-001UPB-B0; Tue, 05 Apr 2022 14:36:47 +0000 Received: from smtp-out1.suse.de ([195.135.220.28]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nbkIV-001UNl-Jz; Tue, 05 Apr 2022 14:36:45 +0000 Received: from relay2.suse.de (relay2.suse.de [149.44.160.134]) by smtp-out1.suse.de (Postfix) with ESMTP id EA076210E5; Tue, 5 Apr 2022 14:36:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1649169399; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=kSbep7KEvKMw5NA9dGHZ82B+/h6ENrK0h+ktGBnoonA=; b=HkEw9NRuL/3L34R2MOn6s81P7RCjKI+svCy8UEL8/p1egYa/TLjM/Di4T8JbZ+JWkLZbbY 8KCdOqQyeK7SiD6m2NSd31cOFh+hO2QZg7v7aoibmkdtF5eErEqoWcx8YM6b9t+4AtAH2Q 6g6UQ1Lw5l0W97aLfm5OXZUcrL+Q3BI= Received: from suse.cz (unknown [10.100.224.162]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by relay2.suse.de (Postfix) with ESMTPS id 17E6DA3B93; Tue, 5 Apr 2022 14:36:38 +0000 (UTC) Date: Tue, 5 Apr 2022 16:36:38 +0200 From: Petr Mladek To: Lecopzer Chen Cc: acme@kernel.org, akpm@linux-foundation.org, alexander.shishkin@linux.intel.com, catalin.marinas@arm.com, davem@davemloft.net, jolsa@redhat.com, jthierry@redhat.com, keescook@chromium.org, kernelfans@gmail.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-perf-users@vger.kernel.org, mark.rutland@arm.com, masahiroy@kernel.org, matthias.bgg@gmail.com, maz@kernel.org, mcgrof@kernel.org, mingo@redhat.com, namhyung@kernel.org, nixiaoming@huawei.com, peterz@infradead.org, sparclinux@vger.kernel.org, sumit.garg@linaro.org, wangqing@vivo.com, will@kernel.org, yj.chiang@mediatek.com Subject: Re: [PATCH v3 5/5] arm64: Enable perf events based hard lockup detector Message-ID: References: <20220404141709.GA26840@pathway.suse.cz> <20220405125304.3762-1-lecopzer.chen@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220405125304.3762-1-lecopzer.chen@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220405_073643_845169_752E0A62 X-CRM114-Status: GOOD ( 44.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue 2022-04-05 20:53:04, Lecopzer Chen wrote: > > > On Thu 2022-03-24 22:14:05, Lecopzer Chen wrote: > > > With the recent feature added to enable perf events to use pseudo NMIs > > > as interrupts on platforms which support GICv3 or later, its now been > > > possible to enable hard lockup detector (or NMI watchdog) on arm64 > > > platforms. So enable corresponding support. > > > > > > One thing to note here is that normally lockup detector is initialized > > > just after the early initcalls but PMU on arm64 comes up much later as > > > device_initcall(). To cope with that, overriding watchdog_nmi_probe() to > > > let the watchdog framework know PMU not ready, and inform the framework > > > to re-initialize lockup detection once PMU has been initialized. > > > > > > [1]: http://lore.kernel.org/linux-arm-kernel/1610712101-14929-1-git-send-email-sumit.garg@linaro.org > > > > > > --- /dev/null > > > +++ b/arch/arm64/kernel/watchdog_hld.c > > > @@ -0,0 +1,37 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +#include > > > +#include > > > +#include > > > + > > > +/* > > > + * Safe maximum CPU frequency in case a particular platform doesn't implement > > > + * cpufreq driver. Although, architecture doesn't put any restrictions on > > > + * maximum frequency but 5 GHz seems to be safe maximum given the available > > > + * Arm CPUs in the market which are clocked much less than 5 GHz. On the other > > > + * hand, we can't make it much higher as it would lead to a large hard-lockup > > > + * detection timeout on parts which are running slower (eg. 1GHz on > > > + * Developerbox) and doesn't possess a cpufreq driver. > > > + */ > > > +#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz > > > +u64 hw_nmi_get_sample_period(int watchdog_thresh) > > > +{ > > > + unsigned int cpu = smp_processor_id(); > > > + unsigned long max_cpu_freq; > > > + > > > + max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL; > > > + if (!max_cpu_freq) > > > + max_cpu_freq = SAFE_MAX_CPU_FREQ; > > > + > > > + return (u64)max_cpu_freq * watchdog_thresh; > > > +} > > > > This change is not mentioned in the commit message. > > Please, put it into a separate patch. > > > Actully, This cames from > [1]: http://lore.kernel.org/linux-arm-kernel/1610712101-14929-1-git-send-email-sumit.garg@linaro.org > And I didn't touch the commit message from the origin patch. > But of course, I could imporve it with proper description if > anyone thinks it's not good enough. I see. > Would you mean put this function hw_nmi_get_sample_period() in patch > 6th? > In the view of "arm64 uses delayed init with all the functionality it need to set up", > IMO, this make sense for me to put into a single patch. Or you could split it in two patches and add hw_nmi_get_sample_period() in the earlier patch. > But if you still think this should put into a separate patch, I'll do it:) It is always better to split the changes whenever possible. It makes the review easier. And it also helps to find the real culprit of a regression using bisection. > > > +int __init watchdog_nmi_probe(void) > > > +{ > > > + if (!allow_lockup_detector_init_retry) > > > + return -EBUSY; > > > > How do you know that you should return -EBUSY > > when retry in not enabled? > > > > I guess that it is an optimization to make it fast > > during the first call. But the logic is far from > > obvious. > > > > Yes, you can see this as an optimization, because arm64 PMU is not ready > during lockup_detector_init(), so the watchdog_nmi_probe() must fail. > > Thus we only want to do watchdog_nmi_probe() in delayed init, > so if not in the state (allow_lockup_detector_init_retry=true), just tell > > if it's unclear Yes, it is far from obvious. > maybe a brief comment can be add like this: > > + /* arm64 is only able to initialize lockup detecor during delayed init */ > + if (!allow_lockup_detector_init_retry) > + return -EBUSY; No, please, remove this optimization. It just makes problems: + it requires a comment here because the logic is far from obvious. + it is the reason why we need another variable to avoid the race in lockup_detector_check(), see the discussion about the 4th patch. > > > + > > > + if (!arm_pmu_irq_is_nmi()) > > > + return -ENODEV; > > > + > > > + return hardlockup_detector_perf_init(); > > > +} > > > For arm_pmu_irq_is_nmi() checking, we do need it, becasue arm64 needs > explictly turns on Pseudo-NMI to support base function for NMI. > > hardlockup_detector_perf_init() will success even if we haven't had > Pseudo-NMI turns on, however, the pmu interrupts will act like a > normal interrupt instead of NMI and the hardlockup detector would be broken. I see. Please, explain this in a comment. It is another thing that is far from obvious. Best Regards, Petr _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel