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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id pp23-20020a0568709d1700b000e2d876505dsm406800oab.32.2022.04.20.14.30.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Apr 2022 14:30:25 -0700 (PDT) Received: (nullmailer pid 1882568 invoked by uid 1000); Wed, 20 Apr 2022 21:30:24 -0000 Date: Wed, 20 Apr 2022 16:30:24 -0500 From: Rob Herring To: Tomi Valkeinen Cc: Jyri Sarha , Vignesh Raghavendra , Nishanth Menon , DRI Development , Devicetree , Linux ARM Kernel , Linux Kernel , Nikhil Devshatwar , Aradhya Bhatia Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Message-ID: References: <20220419070302.16502-1-a-bhatia1@ti.com> <20220419070302.16502-2-a-bhatia1@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220420_143030_164272_02A32D7C X-CRM114-Status: GOOD ( 20.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote: > Hi, > > On 19/04/2022 17:20, Rob Herring wrote: > > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote: > > > The DSS IP on the ti-am65x soc supports an additional register space, > > > named "common1". Further. the IP services a maximum number of 2 > > > interrupts. > > > > > > Add the missing register space "common1" and the additional interrupt. > > > > > > Signed-off-by: Aradhya Bhatia > > > --- > > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++--- > > > 1 file changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > index 5c7d2cbc4aac..102059e9e0d5 100644 > > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml > > > @@ -26,6 +26,7 @@ properties: > > > Addresses to each DSS memory region described in the SoC's TRM. > > > items: > > > - description: common DSS register area > > > + - description: common1 DSS register area > > > > You've just broken the ABI. > > > > New entries have to go on the end. > > I'm curious, if the 'reg-names' is a required property, as it is here, does > this still break the ABI? Yes, the order is part of the ABI. Sometimes we just give up with multiple optional entries or inherited any order allowed, but here there is no reason. Just add 'common1' to the end. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel