From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI
Date: Thu, 21 Apr 2022 10:36:07 +0100 [thread overview]
Message-ID: <YmElh0VjHGHGYmCO@FVFF77S0Q05N> (raw)
In-Reply-To: <20220419104329.188489-4-broonie@kernel.org>
On Tue, Apr 19, 2022 at 11:43:24AM +0100, Mark Brown wrote:
> We already use lower case in some defines in sysreg.h, for consistency with
> the architecture definition do so for SCTLR_EL1.nTWE and SCTLR_EL1.nTWI.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
I have no strong feelings either way as to whether we should keep this all caps
or match the architectural CamelCase, so:
Acked-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> ---
> arch/arm64/include/asm/sysreg.h | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 1911f36773e5..f300c49d6281 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -689,8 +689,8 @@
> #define SCTLR_EL1_UCI (BIT(26))
> #define SCTLR_EL1_E0E (BIT(24))
> #define SCTLR_EL1_SPAN (BIT(23))
> -#define SCTLR_EL1_NTWE (BIT(18))
> -#define SCTLR_EL1_NTWI (BIT(16))
> +#define SCTLR_EL1_nTWE (BIT(18))
> +#define SCTLR_EL1_nTWI (BIT(16))
> #define SCTLR_EL1_UCT (BIT(15))
> #define SCTLR_EL1_DZE (BIT(14))
> #define SCTLR_EL1_UMA (BIT(9))
> @@ -714,7 +714,7 @@
> #define INIT_SCTLR_EL1_MMU_ON \
> (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | \
> SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE | SCTLR_EL1_UCT | \
> - SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
> + SCTLR_EL1_nTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
> ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
>
> /* MAIR_ELx memory attributes (used by Linux) */
> --
> 2.30.2
>
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next prev parent reply other threads:[~2022-04-21 9:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 10:43 [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Brown
2022-04-19 10:43 ` [PATCH v4 1/8] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-04-21 9:33 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-21 9:35 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-21 9:36 ` Mark Rutland [this message]
2022-04-19 10:43 ` [PATCH v4 4/8] arm64: Add sysreg header generation scripting Mark Brown
2022-04-21 9:47 ` Mark Rutland
2022-04-21 13:00 ` Mark Brown
2022-04-21 14:16 ` Mark Rutland
2022-04-21 14:50 ` Mark Brown
2022-04-21 15:35 ` Mark Rutland
2022-04-21 15:46 ` Mark Brown
2022-04-19 10:43 ` [PATCH v4 5/8] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-21 9:52 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-21 9:58 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-21 9:59 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-04-21 10:05 ` Mark Rutland
2022-04-22 12:14 ` Mark Brown
2022-04-22 13:42 ` Mark Rutland
2022-04-22 13:50 ` Mark Brown
2022-04-21 10:15 ` [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Rutland
2022-04-21 15:14 ` Mark Brown
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