From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1
Date: Thu, 21 Apr 2022 10:59:46 +0100 [thread overview]
Message-ID: <YmErEj8OtYSsxSjT@FVFF77S0Q05N> (raw)
In-Reply-To: <20220419104329.188489-8-broonie@kernel.org>
On Tue, Apr 19, 2022 at 11:43:28AM +0100, Mark Brown wrote:
> Automatically generate definitions for accessing the TTBR0_EL1 registers,
> no functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Thanks,
Mark.
> ---
> arch/arm64/include/asm/sysreg.h | 2 --
> arch/arm64/tools/sysreg | 12 ++++++++++++
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 2b5cc67b3bc3..b9023797a5b9 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -212,8 +212,6 @@
> #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0)
> #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
>
> -#define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
> -#define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
> #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
>
> #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 040745387528..f6195ccbf9b8 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -99,3 +99,15 @@ Enum 7:4 AES
> EndEnum
> Res0 3:0
> EndSysreg
> +
> +Sysreg TTBR0_EL1 3 0 2 0 0
> +Field 63:48 ASID
> +Field 47:1 BADDR
> +Field 0 CnP
> +EndSysreg
> +
> +Sysreg TTBR1_EL1 3 0 2 0 1
> +Field 63:48 ASID
> +Field 47:1 BADDR
> +Field 0 CnP
> +EndSysreg
> --
> 2.30.2
>
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next prev parent reply other threads:[~2022-04-21 10:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 10:43 [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Brown
2022-04-19 10:43 ` [PATCH v4 1/8] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-04-21 9:33 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-21 9:35 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-21 9:36 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 4/8] arm64: Add sysreg header generation scripting Mark Brown
2022-04-21 9:47 ` Mark Rutland
2022-04-21 13:00 ` Mark Brown
2022-04-21 14:16 ` Mark Rutland
2022-04-21 14:50 ` Mark Brown
2022-04-21 15:35 ` Mark Rutland
2022-04-21 15:46 ` Mark Brown
2022-04-19 10:43 ` [PATCH v4 5/8] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-21 9:52 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-21 9:58 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-21 9:59 ` Mark Rutland [this message]
2022-04-19 10:43 ` [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-04-21 10:05 ` Mark Rutland
2022-04-22 12:14 ` Mark Brown
2022-04-22 13:42 ` Mark Rutland
2022-04-22 13:50 ` Mark Brown
2022-04-21 10:15 ` [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Rutland
2022-04-21 15:14 ` Mark Brown
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