From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDBBDC433EF for ; Thu, 21 Apr 2022 10:06:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=IGMVq0CyHnaj6ZN5Fs/HR47kowLaL88Q6MndRe76mW4=; b=s72Y0zw8R+OIvT SGqxxFELNlbnOuRnHPiT07EGeEiRKWAaxqe+c8aPWLUp6HGoUnh626JSc3rZ3h9HNNv+Ywu6PQu58 fvzHMawuSauuvNgugPmUWfh374N1pUgG4pMqlmH+j8ql745Gb75OlbL9XjU/5Av8HoPUwB1CZUWr1 NwkKyTb1UKGvQhhRmSAW9XOM41bpzCQ4QXTFLCaSNmQBA3Tg1bU9+3LZ7Eh6Gh6v/oRnZmqYo5W2V +7x11jJKLXdXDP2i5r9GWqNkkGx+5k9F0mNS/RGAbyIhucGegDlyTDx04uGT84YZ+LI1Q7xpgwwql LDCBrrzikFzB9im4Is3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhTh1-00CwEH-Hf; Thu, 21 Apr 2022 10:05:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhTgx-00CwCJ-QA for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2022 10:05:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B1C81477; Thu, 21 Apr 2022 03:05:32 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.76.146]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 84DC73F766; Thu, 21 Apr 2022 03:05:31 -0700 (PDT) Date: Thu, 21 Apr 2022 11:05:27 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Message-ID: References: <20220419104329.188489-1-broonie@kernel.org> <20220419104329.188489-9-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220419104329.188489-9-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220421_030540_011116_E46127ED X-CRM114-Status: GOOD ( 19.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 19, 2022 at 11:43:29AM +0100, Mark Brown wrote: > Automatically generate register definitions for SCTLR_EL1. No functional > change. > > Several fields which are defined in the current revision of DDI0487 but > which are not yet used by the kernel are left as RES1 in order to ensure > that the SCTLR_EL1_RES1 mask used for early initialisation of SCTLR_EL1 is > not changed. These are LSMAOE, nTLSMD, EIS, TSCXT and EOS. I think that going forward we'll hit similar issues when adding new fields, so we probably want to distinguish "architecturally RESx" and "The kernel wants to treat these as RESx". I suspect we should add those fields to the scripting, but (manually) add a definition to a header with both the architectural RES1 bits and the bits we're treating as RES1 even though they're now been allocated a purpose. I'm not sure how to name that clearly, though. Otherwise, this looks good to me. Thanks, Mark. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 29 -------------- > arch/arm64/tools/sysreg | 70 +++++++++++++++++++++++++++++++++ > 2 files changed, 70 insertions(+), 29 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index b9023797a5b9..63b545260e62 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -203,7 +203,6 @@ > #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) > #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) > > -#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) > #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) > #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) > #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) > @@ -679,34 +678,6 @@ > (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) > > /* SCTLR_EL1 specific flags. */ > -#define SCTLR_EL1_EPAN (BIT(57)) > -#define SCTLR_EL1_ATA0 (BIT(42)) > - > -#define SCTLR_EL1_TCF0_SHIFT 38 > -#define SCTLR_EL1_TCF0_NONE UL(0x0) > -#define SCTLR_EL1_TCF0_SYNC UL(0x1) > -#define SCTLR_EL1_TCF0_ASYNC UL(0x2) > -#define SCTLR_EL1_TCF0_ASYMM UL(0x3) > -#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT) > - > -#define SCTLR_EL1_BT1 (BIT(36)) > -#define SCTLR_EL1_BT0 (BIT(35)) > -#define SCTLR_EL1_UCI (BIT(26)) > -#define SCTLR_EL1_E0E (BIT(24)) > -#define SCTLR_EL1_SPAN (BIT(23)) > -#define SCTLR_EL1_nTWE (BIT(18)) > -#define SCTLR_EL1_nTWI (BIT(16)) > -#define SCTLR_EL1_UCT (BIT(15)) > -#define SCTLR_EL1_DZE (BIT(14)) > -#define SCTLR_EL1_UMA (BIT(9)) > -#define SCTLR_EL1_SED (BIT(8)) > -#define SCTLR_EL1_ITD (BIT(7)) > -#define SCTLR_EL1_CP15BEN (BIT(5)) > -#define SCTLR_EL1_SA0 (BIT(4)) > - > -#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ > - (BIT(29))) > - > #ifdef CONFIG_CPU_BIG_ENDIAN > #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) > #else > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index f6195ccbf9b8..6248cfbf5288 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -100,6 +100,76 @@ EndEnum > Res0 3:0 > EndSysreg > > +Sysreg SCTLR_EL1 3 0 1 9 9 > +Field 63 TIDCP > +Field 62 SPINMASK > +Field 61 NMI > +Field 60 EnTP2 > +Res0 59:58 > +Field 57 EPAN > +Field 56 EnALS > +Field 55 EnAS0 > +Field 54 EnASR > +Field 53 TME > +Field 52 TME0 > +Field 51 TMT > +Field 50 TMT0 > +Field 49:46 TWEDEL > +Field 45 TWEDEn > +Field 44 DSSBS > +Field 43 ATA > +Field 42 ATA0 > +Enum 41:40 TCF > + 0b00 NONE > + 0b01 SYNC > + 0b10 ASYNC > + 0b11 ASYMM > +EndEnum > +Enum 39:38 TCF0 > + 0b00 NONE > + 0b01 SYNC > + 0b10 ASYNC > + 0b11 ASYMM > +EndEnum > +Field 37 ITFSB > +Field 36 BT1 > +Field 35 BT0 > +Res0 34 > +Field 33 MSCEn > +Field 32 CMOW > +Field 31 EnIA > +Field 30 EnIB > +Res1 29:28 > +Field 27 EnDA > +Field 26 UCI > +Field 25 EE > +Field 24 E0E > +Field 23 SPAN > +Res1 22 > +Field 21 IESB > +Res1 20 > +Field 19 WXN > +Field 18 nTWE > +Res0 17 > +Field 16 nTWI > +Field 15 UCT > +Field 14 DZE > +Field 13 EnDB > +Field 12 I > +Res1 11 > +Field 10 EnRCTX > +Field 9 UMA > +Field 8 SED > +Field 7 ITD > +Field 6 nAA > +Field 5 CP15BEN > +Field 4 SA0 > +Field 3 SA > +Field 2 C > +Field 1 A > +Field 0 M > +EndSysreg > + > Sysreg TTBR0_EL1 3 0 2 0 0 > Field 63:48 ASID > Field 47:1 BADDR > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel