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From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1
Date: Fri, 22 Apr 2022 14:42:30 +0100	[thread overview]
Message-ID: <YmKwxq2i8UrzQjRw@lakrids> (raw)
In-Reply-To: <YmKcO9MLbgNTfvpl@sirena.org.uk>

On Fri, Apr 22, 2022 at 01:14:51PM +0100, Mark Brown wrote:
> On Thu, Apr 21, 2022 at 11:05:27AM +0100, Mark Rutland wrote:
> > On Tue, Apr 19, 2022 at 11:43:29AM +0100, Mark Brown wrote:
> 
> > > Several fields which are defined in the current revision of DDI0487 but
> > > which are not yet used by the kernel are left as RES1 in order to ensure
> > > that the SCTLR_EL1_RES1 mask used for early initialisation of SCTLR_EL1 is
> > > not changed. These are LSMAOE, nTLSMD, EIS, TSCXT and EOS.
> 
> > I think that going forward we'll hit similar issues when adding new fields, so
> > we probably want to distinguish "architecturally RESx" and "The kernel wants to
> > treat these as RESx".
> 
> > I suspect we should add those fields to the scripting, but (manually) add a
> > definition to a header with both the architectural RES1 bits and the bits we're
> > treating as RES1 even though they're now been allocated a purpose.
> 
> > I'm not sure how to name that clearly, though.
> 
> I think I'd come to a similar conclusion but as you say the naming is
> annoying and in cases like these ones there's so few users and they're
> oring in other bits so it might be more sensible to just or in these now
> defined RES1 bits in the user, skipping out on the naming question
> entirely - in this case the usage is in INIT_SCTLR_EL2_MMU_*.  Looking
> at it again now I'm inclined to go that way for this one.

FWIW, I'm perfectly happy with adding those bits explicitly in the
`INIT_SCTLR_EL*` definitions. The key thing I wanted is that as a
policy, `<regname>_RES1` is purely the architecturally RES1 bits.

Thanks,
Mark.

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  reply	other threads:[~2022-04-22 13:43 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-19 10:43 [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Brown
2022-04-19 10:43 ` [PATCH v4 1/8] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-04-21  9:33   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-21  9:35   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-21  9:36   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 4/8] arm64: Add sysreg header generation scripting Mark Brown
2022-04-21  9:47   ` Mark Rutland
2022-04-21 13:00     ` Mark Brown
2022-04-21 14:16       ` Mark Rutland
2022-04-21 14:50         ` Mark Brown
2022-04-21 15:35           ` Mark Rutland
2022-04-21 15:46             ` Mark Brown
2022-04-19 10:43 ` [PATCH v4 5/8] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-21  9:52   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-21  9:58   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-21  9:59   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-04-21 10:05   ` Mark Rutland
2022-04-22 12:14     ` Mark Brown
2022-04-22 13:42       ` Mark Rutland [this message]
2022-04-22 13:50         ` Mark Brown
2022-04-21 10:15 ` [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Rutland
2022-04-21 15:14   ` Mark Brown

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