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Fri, 22 Apr 2022 09:29:01 -0700 (PDT) Date: Fri, 22 Apr 2022 18:28:58 +0200 From: Thierry Reding To: Sean Anderson Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , Mubin Usman Sayyed , linux-arm-kernel@lists.infradead.org, Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , michal.simek@xilinx.com, Alvaro Gamez , Rob Herring Subject: Re: [PATCH v14 1/2] dt-bindings: pwm: Add Xilinx AXI Timer Message-ID: References: <20220303223544.2810594-1-sean.anderson@seco.com> MIME-Version: 1.0 In-Reply-To: <20220303223544.2810594-1-sean.anderson@seco.com> User-Agent: Mutt/2.2.1 (c8109e14) (2022-02-19) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220422_092907_153218_F5C94EC6 X-CRM114-Status: GOOD ( 27.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============0060605563775549868==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0060605563775549868== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ItmECfP7fegOVQ7B" Content-Disposition: inline --ItmECfP7fegOVQ7B Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Mar 03, 2022 at 05:35:42PM -0500, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a > "soft" block, so it has some parameters which would not be configurable in > most hardware. This binding is usually automatically generated by Xilinx's > tools, so the names and values of some properties should be kept as they > are, if possible. In addition, this binding is already in the kernel at > arch/microblaze/boot/dts/system.dts, and in user software such as QEMU. >=20 > The existing driver uses the clock-frequency property, or alternatively t= he > /cpus/timebase-frequency property as its frequency input. Because these > properties are deprecated, they have not been included with this schema. > All new bindings should use the clocks/clock-names properties to specify > the parent clock. >=20 > Because we need to init timer devices so early in boot, we determine if we > should use the PWM driver or the clocksource/clockevent driver by the > presence/absence, respectively, of #pwm-cells. Because both counters are > used by the PWM, there is no need for a separate property specifying which > counters are to be used for the PWM. >=20 > Signed-off-by: Sean Anderson > Reviewed-by: Rob Herring > --- >=20 > (no changes since v8) >=20 > Changes in v8: > - Set additionalProperties: false >=20 > Changes in v7: > - Add #pwm-cells to properties > - Document why additionalProperties is true >=20 > Changes in v6: > - Enumerate possible counter widths > - Fix incorrect schema id >=20 > Changes in v5: > - Add example for timer binding > - Fix indentation lint > - Move schema into the timer directory > - Remove xlnx,axi-timer-2.0 compatible string > - Update commit message to reflect revisions >=20 > Changes in v4: > - Make some properties optional for clocksource drivers > - Predicate PWM driver on the presence of #pwm-cells > - Remove references to generate polarity so this can get merged >=20 > Changes in v3: > - Add an example with non-deprecated properties only. > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Mark all boolean-as-int properties as deprecated >=20 > Changes in v2: > - Use 32-bit addresses for example binding >=20 > .../bindings/timer/xlnx,xps-timer.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-time= r.yaml Applied, thanks. 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