From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59496C433F5 for ; Tue, 26 Apr 2022 13:01:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TdmjVeiUKbEzZGo0goAeMS9S48tF7Bn1QqKD+BFh1Lg=; b=N01gkXILpOFaaB om++7aXCupQ5rVrDqC9tgQCaN3LaQuJXgwze5dQQxbiDKw8uuXW/ebBt1g7YEBWKt9OCa+TzBTh89 Ex+5QqqJa6cAdZKKyM/MwHbT92YOaxRbVmyNRZTfS+w7p/ZQb3iqxuFyxGQxi5CQfj3nUrY5vl75r 4ggsn1SVDfMmqVn6oSXXJj7zye8V0oiUTPVx5UtkiPVvDTUq5ygvaUnjHrVJFJCSGJkflxfe0U69h eKMzCLBnytTXRmZfgoH0mtOkYq4b87mTAr+JxWU2ogf2ims0lrzqcl+UCqogLNePjQz9JrwvVtTbF o/U18T3d7zbCkaZMJCxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njKnz-00EQMf-Qa; Tue, 26 Apr 2022 13:00:36 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1njKeR-00EMNS-Pp for linux-arm-kernel@lists.infradead.org; Tue, 26 Apr 2022 12:50:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7925B23A; Tue, 26 Apr 2022 05:50:42 -0700 (PDT) Received: from lakrids (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9096C3F774; Tue, 26 Apr 2022 05:50:41 -0700 (PDT) Date: Tue, 26 Apr 2022 13:50:39 +0100 From: Mark Rutland To: Marco Elver , will@kernel.org Cc: Kefeng Wang , catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: kcsan: Fix kcsan test_barrier fail and panic Message-ID: References: <20220426081700.1376542-1-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_055043_940110_3A4691A4 X-CRM114-Status: GOOD ( 18.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 26, 2022 at 02:10:06PM +0200, Marco Elver wrote: > On Tue, Apr 26, 2022 at 08:17AM +0000, Kefeng Wang wrote: > > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > > index fd7e8fbaeef1..18863c50e9ce 100644 > > --- a/include/asm-generic/barrier.h > > +++ b/include/asm-generic/barrier.h > > @@ -38,6 +38,10 @@ > > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > > #endif > > > > +#ifdef __dma_mb > > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > > +#endif > > + > > So it looks like arm64 is the only arch that defines dma_mb(). By adding > it to asm-generic, we'd almost be encouraging other architectures to add > it, which I don't know we want. > > Documentation/memory-barriers.txt doesn't mention dma_mb() either - so > perhaps dma_mb() doesn't belong in asm-generic/barrier.h, and you could > only change arm64's definition of dma_mb() to add the kcsan_mb(). > > Preferences? Maybe arch64 maintainers have more background on why arm64 > is an anomaly here. Looking around, there's a single user: [mark@lakrids:~/src/linux]% git grep -w dma_mb arch/arm64/include/asm/barrier.h:#define dma_mb() dmb(osh) arch/arm64/include/asm/io.h:#define __iomb() dma_mb() [mark@lakrids:~/src/linux]% git grep -w __iomb arch/arm64/include/asm/io.h:#define __iomb() dma_mb() drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: __iomb(); ... and that was introduced in commit: a76a37777f2c936b ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer") ... where it is used to ensure that prior (read and write) accesses to memory by a CPU are ordered w.r.t. a subsequent MMIO write. That seems like it could be a generic shape of problem (especially for IOMMUs), even if arm64 is the only architecture with an implementation today. From my PoV it would weem to make sense as a generic thing, and should probably be added to Documentation/memory-barriers.txt. Will, thoughts? Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel