Re: [PATCH 1/2] clk: imx8mp: Enable no longer handled gates

From: Abel Vesa <abel.vesa@nxp.com>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: linux-clk@vger.kernel.org, Stephen Boyd <sboyd@kernel.org>,
	Shawn Guo <shawnguo@kernel.org>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	NXP Linux Team <linux-imx@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	David Jander <david@protonic.nl>
Subject: Re: [PATCH 1/2] clk: imx8mp: Enable no longer handled gates
Date: Wed, 27 Apr 2022 15:51:41 +0300	[thread overview]
Message-ID: <Ymk8XRS/BSCy6byS@abelvesa> (raw)
In-Reply-To: <20220425095249.259406-2-s.hauer@pengutronix.de>

On 22-04-25 11:52:48, Sascha Hauer wrote:
> Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL
> was removed in d097cc045b649. We shouldn't assume these gates are at
> their reset-default enabled state. Enable them to let the kernel work
> when the bootloader has changed the values.
>
> Fixes: d097cc045b649 ("clk: imx8mp: remove SYS PLL 1/2 clock gates")
> Reported-by: David Jander <david@protonic.nl>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/clk/imx/clk-imx8mp.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 18f5b7c3ca9d8..10446a1b509e7 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -407,6 +407,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct device_node *np;
>  	void __iomem *anatop_base, *ccm_base;
> +	u32 val;
>
>  	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
>  	anatop_base = of_iomap(np, 0);
> @@ -480,6 +481,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
>  	hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
>
> +	/*
> +	 * The gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL are not handled by the
> +	 * driver, make sure they are all enabled.
> +	 */
> +	val = readl(anatop_base + 0x94);
> +	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
> +	       BIT(25) | BIT(27);

The same bits are used for PLL1 and PLL2, so maybe have a single define
containing all bits and use it in both places. Might look cleaner.

> +	writel(val, anatop_base + 0x94);
> +
>  	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
>
>  	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> @@ -494,6 +504,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>
>  	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
>
> +	/*
> +	 * The gates in CCM_ANALOG_SYS_PLL2_GEN_CTRL are not handled by the
> +	 * driver, make sure they are all enabled.
> +	 */
> +	val = readl(anatop_base + 0x104);
> +	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
> +	       BIT(25) | BIT(27);
> +	writel(val, anatop_base + 0x104);
> +
>  	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
>  	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
>  	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> --
> 2.30.2
>

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