[PATCH 0/2] clk: i.MX8M[PQ] fixes

[PATCH 0/2] clk: i.MX8M[PQ] fixes

[Sascha Hauer]

This series has two fixes for the i.MX8MP and i.MX8MQ clk support. It
was decided that the gates of the divided outputs of the System PLLs
are not useful for the Kernel and so the gate clocks were removed.
Nevertheless they are of course still there in hardware and the Kernel
needs them to be enabled for the consumers hanging on these gates.
Enable them explicitly instead of assuming that the gates are still
at their reset default on state.

Sascha

Sascha Hauer (2):
  clk: imx8mp: Enable no longer handled gates
  clk: imx8mq: Enable no longer handled gates

 drivers/clk/imx/clk-imx8mp.c | 19 +++++++++++++++++++
 drivers/clk/imx/clk-imx8mq.c | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+)

-- 
2.30.2


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[PATCH 1/2] clk: imx8mp: Enable no longer handled gates

[Sascha Hauer]

Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL
was removed in d097cc045b649. We shouldn't assume these gates are at
their reset-default enabled state. Enable them to let the kernel work
when the bootloader has changed the values.

Fixes: d097cc045b649 ("clk: imx8mp: remove SYS PLL 1/2 clock gates")
Reported-by: David Jander <david@protonic.nl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mp.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 18f5b7c3ca9d8..10446a1b509e7 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -407,6 +407,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *np;
 	void __iomem *anatop_base, *ccm_base;
+	u32 val;
 
 	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
 	anatop_base = of_iomap(np, 0);
@@ -480,6 +481,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
 	hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL are not handled by the
+	 * driver, make sure they are all enabled.
+	 */
+	val = readl(anatop_base + 0x94);
+	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
+	       BIT(25) | BIT(27);
+	writel(val, anatop_base + 0x94);
+
 	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
 
 	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
@@ -494,6 +504,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 
 	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL2_GEN_CTRL are not handled by the
+	 * driver, make sure they are all enabled.
+	 */
+	val = readl(anatop_base + 0x104);
+	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
+	       BIT(25) | BIT(27);
+	writel(val, anatop_base + 0x104);
+
 	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
 	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
 	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
-- 
2.30.2


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Re: [PATCH 1/2] clk: imx8mp: Enable no longer handled gates

[Abel Vesa]

On 22-04-25 11:52:48, Sascha Hauer wrote:
> Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL
> was removed in d097cc045b649. We shouldn't assume these gates are at
> their reset-default enabled state. Enable them to let the kernel work
> when the bootloader has changed the values.
>
> Fixes: d097cc045b649 ("clk: imx8mp: remove SYS PLL 1/2 clock gates")
> Reported-by: David Jander <david@protonic.nl>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/clk/imx/clk-imx8mp.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 18f5b7c3ca9d8..10446a1b509e7 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -407,6 +407,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	struct device *dev = &pdev->dev;
>  	struct device_node *np;
>  	void __iomem *anatop_base, *ccm_base;
> +	u32 val;
>
>  	np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
>  	anatop_base = of_iomap(np, 0);
> @@ -480,6 +481,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>  	hws[IMX8MP_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11);
>  	hws[IMX8MP_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11);
>
> +	/*
> +	 * The gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL are not handled by the
> +	 * driver, make sure they are all enabled.
> +	 */
> +	val = readl(anatop_base + 0x94);
> +	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
> +	       BIT(25) | BIT(27);

The same bits are used for PLL1 and PLL2, so maybe have a single define
containing all bits and use it in both places. Might look cleaner.

> +	writel(val, anatop_base + 0x94);
> +
>  	hws[IMX8MP_SYS_PLL1_OUT] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11);
>
>  	hws[IMX8MP_SYS_PLL1_40M] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);
> @@ -494,6 +504,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
>
>  	hws[IMX8MP_SYS_PLL2_OUT] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11);
>
> +	/*
> +	 * The gates in CCM_ANALOG_SYS_PLL2_GEN_CTRL are not handled by the
> +	 * driver, make sure they are all enabled.
> +	 */
> +	val = readl(anatop_base + 0x104);
> +	val |= BIT(13) | BIT(15) | BIT(17) | BIT(19) | BIT(21) | BIT(23) |
> +	       BIT(25) | BIT(27);
> +	writel(val, anatop_base + 0x104);
> +
>  	hws[IMX8MP_SYS_PLL2_50M] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20);
>  	hws[IMX8MP_SYS_PLL2_100M] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10);
>  	hws[IMX8MP_SYS_PLL2_125M] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8);
> --
> 2.30.2
>

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[PATCH 2/2] clk: imx8mq: Enable no longer handled gates

[Sascha Hauer]

Handling of the divided pll output gates in CCM_ANALOG_SYS_PLL1_GEN_CTRL
was removed in c586f53ae159c. We shouldn't assume these gates are at
their reset-default enabled state. Enable them to let the kernel work
when the bootloader has changed the values.

Fixes: c586f53ae159c ("clk: imx8mq: remove SYS PLL 1/2 clock gates")
Reported-by: David Jander <david@protonic.nl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/imx/clk-imx8mq.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 83cc2b1c32947..55b72ff0c6a41 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -286,6 +286,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
 	void __iomem *base;
+	u32 val;
 	int err;
 
 	clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
@@ -357,6 +358,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_DRAM_PLL_OUT] = imx_clk_hw_sscg_pll("dram_pll_out", dram_pll_out_sels, ARRAY_SIZE(dram_pll_out_sels), 0, 0, 0, base + 0x60, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
 	hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL_CFG0 are not handled by the driver,
+	 * make sure they are all enabled.
+	 */
+	val = readl(base + 0x30);
+	val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) |
+	       BIT(21) | BIT(23) | BIT(25);
+	writel(val, base + 0x30);
+
 	/* SYS PLL1 fixed output */
 	hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);
 	hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);
@@ -368,6 +378,15 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);
 	hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);
 
+	/*
+	 * The gates in CCM_ANALOG_SYS_PLL2_CFG0 are not handled by the driver,
+	 * make sure they are all enabled.
+	 */
+	val = readl(base + 0x3c);
+	val |= BIT(9) | BIT(11) | BIT(13) | BIT(15) | BIT(17) | BIT(19) |
+	       BIT(21) | BIT(23) | BIT(25);
+	writel(val, base + 0x3c);
+
 	/* SYS PLL2 fixed output */
 	hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);
 	hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);
-- 
2.30.2


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