From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR
Date: Fri, 13 May 2022 15:41:38 +0100 [thread overview]
Message-ID: <Yn5uIuX1Okk3IvuK@lakrids> (raw)
In-Reply-To: <20220510161208.631259-12-broonie@kernel.org>
On Tue, May 10, 2022 at 05:12:07PM +0100, Mark Brown wrote:
> Convert SVCR to automatic generation, no functional change.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 4 ----
> arch/arm64/tools/sysreg | 6 ++++++
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index b4affc3fd569..804b5326c393 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -474,10 +474,6 @@
> #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
> #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
>
> -#define SYS_SVCR sys_reg(3, 3, 4, 2, 2)
> -#define SVCR_ZA_MASK 2
> -#define SVCR_SM_MASK 1
> -
> #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
> #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
> #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index d29bc429f504..7888603db50a 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -211,6 +211,12 @@ Res0 14:12
> Field 11:0 AFFINITY
> EndSysreg
>
> +Sysreg SVCR 3 3 4 2 2
> +Res0 63:2
> +Field 1 ZA
> +Field 0 SM
> +EndSysreg
These all look right to me per ARM DDI 0487H.a, section C5.2.25, pages
C5-747 to C5-749.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Mark.
> +
> Sysreg SMPRIMAP_EL2 3 4 1 2 5
> Field 63:60 P15
> Field 59:56 P14
> --
> 2.30.2
>
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next prev parent reply other threads:[~2022-05-13 14:42 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 16:11 [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Mark Brown
2022-05-10 16:11 ` [PATCH v1 01/12] arm64/fp: Make SVE and SME length register definition match architecture Mark Brown
2022-05-10 16:11 ` [PATCH v1 02/12] arm64/fp: Rename SVE and SME LEN field name to _WIDTH Mark Brown
2022-05-10 16:11 ` [PATCH v1 03/12] arm64/sme: Drop SYS_ from SMIDR_EL1 defines Mark Brown
2022-05-10 16:12 ` [PATCH v1 04/12] arm64/sme: Standardise bitfield names for SVCR Mark Brown
2022-05-10 16:12 ` [PATCH v1 05/12] arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h Mark Brown
2022-05-13 14:16 ` Mark Rutland
2022-05-13 19:39 ` Mark Brown
2022-05-10 16:12 ` [PATCH v1 06/12] arm64/sysreg: Support generation of RAZ fields Mark Brown
2022-05-13 14:18 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 07/12] arm64/sme: Automatically generate defines for SMCR Mark Brown
2022-05-13 14:31 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 08/12] arm64/sme: Automatically generate SMIDR_EL1 defines Mark Brown
2022-05-13 14:35 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 09/12] arm64/sme: Automatically generate SMPRIMAP_EL2 definitions Mark Brown
2022-05-13 14:38 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 10/12] arm64/sme: Generate SMPRI_EL1 definitions Mark Brown
2022-05-13 14:39 ` Mark Rutland
2022-05-10 16:12 ` [PATCH v1 11/12] arm64/sme: Generate defintions for SVCR Mark Brown
2022-05-13 14:41 ` Mark Rutland [this message]
2022-05-10 16:12 ` [PATCH v1 12/12] arm64/sve: Generate ZCR definitions Mark Brown
2022-05-13 14:46 ` Mark Rutland
2022-05-16 19:08 ` [PATCH v1 00/12] arm64/fp: Generate definitons for floating point system registers Catalin Marinas
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