From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 47337C433EF for ; Wed, 4 May 2022 13:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sT1/ASkpIilhLdPNQzrsswLEl+Z0qRm9hCDVI1GGNtE=; b=HQQgYe+i4v0IfC eRej1v+afjZXwx14dP+wEFeoLA+azkKgvA3NgrJ+fgiu5eY6faJtTaA48hF2SNGanZ5Zpev6kZ71Y 35iSs2zfvV1kIcBgQZnzTYE9QPliO/7WdTv/RgbABHscplTyuogmnVBwH1OCWCxkTX+QcYMTYYbMp y/eAYGHY+ylh9j/5T91GT2k3Bal+vtl0W8oyhCcNaHFNYc3fiiN+LEk6PX8tYllW9phIQh3SE4MYM yoOOM5po4fKoAW6YLgRQBdmFXOWpB5rR6KdLN/hsfWS0wE0aksW1PQAKmVHVdWF26nI2pflI7JK+x T9H3B+siDrjQ1r5iUqCA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmF1y-00B50w-80; Wed, 04 May 2022 13:27:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmF1u-00B4zB-NF for linux-arm-kernel@lists.infradead.org; Wed, 04 May 2022 13:27:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BE1141042; Wed, 4 May 2022 06:26:56 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.1.13]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8DD883FA49; Wed, 4 May 2022 06:26:55 -0700 (PDT) Date: Wed, 4 May 2022 14:26:47 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 03/12] arm64/mte: Make TCF field values and naming more standard Message-ID: References: <20220503170233.507788-1-broonie@kernel.org> <20220503170233.507788-4-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220503170233.507788-4-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_062658_880186_836474AF X-CRM114-Status: GOOD ( 23.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 03, 2022 at 06:02:24PM +0100, Mark Brown wrote: > In preparation for automatic generation of the defines for system registers > make the values used for the enumeration in SCTLR_ELx.TCF suitable for use > with the newly defined SYS_FIELD_PREP_ENUM helper, removing the shift from > the define and using the helper to generate it on use instead. Since we > only ever interact with this field in EL1 and in preparation for generation > of the defines also rename from SCTLR_ELx to SCTLR_EL1. SCTLR_EL2 is not > quite the same as SCTLR_EL1 so the conversion does not share the field > definitions. > > There should be no functional change from this patch. > > Signed-off-by: Mark Brown Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/sysreg.h | 14 +++++++------- > arch/arm64/kernel/mte.c | 9 +++++---- > arch/arm64/mm/fault.c | 3 ++- > 3 files changed, 14 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 6dc840be0268..732d84111d9f 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -631,13 +631,6 @@ > #define SCTLR_ELx_DSSBS (BIT(44)) > #define SCTLR_ELx_ATA (BIT(43)) > > -#define SCTLR_ELx_TCF_SHIFT 40 > -#define SCTLR_ELx_TCF_NONE (UL(0x0) << SCTLR_ELx_TCF_SHIFT) > -#define SCTLR_ELx_TCF_SYNC (UL(0x1) << SCTLR_ELx_TCF_SHIFT) > -#define SCTLR_ELx_TCF_ASYNC (UL(0x2) << SCTLR_ELx_TCF_SHIFT) > -#define SCTLR_ELx_TCF_ASYMM (UL(0x3) << SCTLR_ELx_TCF_SHIFT) > -#define SCTLR_ELx_TCF_MASK (UL(0x3) << SCTLR_ELx_TCF_SHIFT) > - > #define SCTLR_ELx_ENIA_SHIFT 31 > > #define SCTLR_ELx_ITFSB (BIT(37)) > @@ -677,6 +670,13 @@ > #define SCTLR_EL1_EPAN (BIT(57)) > #define SCTLR_EL1_ATA0 (BIT(42)) > > +#define SCTLR_EL1_TCF_SHIFT 40 > +#define SCTLR_EL1_TCF_NONE (UL(0x0)) > +#define SCTLR_EL1_TCF_SYNC (UL(0x1)) > +#define SCTLR_EL1_TCF_ASYNC (UL(0x2)) > +#define SCTLR_EL1_TCF_ASYMM (UL(0x3)) > +#define SCTLR_EL1_TCF_MASK (UL(0x3) << SCTLR_EL1_TCF_SHIFT) > + > #define SCTLR_EL1_TCF0_SHIFT 38 > #define SCTLR_EL1_TCF0_NONE (UL(0x0)) > #define SCTLR_EL1_TCF0_SYNC (UL(0x1)) > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 41469b69a48e..98f5e1e13c36 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -106,7 +106,8 @@ int memcmp_pages(struct page *page1, struct page *page2) > static inline void __mte_enable_kernel(const char *mode, unsigned long tcf) > { > /* Enable MTE Sync Mode for EL1. */ > - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, tcf); > + sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, > + SYS_FIELD_PREP(SCTLR_EL1, TCF, tcf)); > isb(); > > pr_info_once("MTE: enabled in %s mode at EL1\n", mode); > @@ -122,12 +123,12 @@ void mte_enable_kernel_sync(void) > WARN_ONCE(system_uses_mte_async_or_asymm_mode(), > "MTE async mode enabled system wide!"); > > - __mte_enable_kernel("synchronous", SCTLR_ELx_TCF_SYNC); > + __mte_enable_kernel("synchronous", SCTLR_EL1_TCF_SYNC); > } > > void mte_enable_kernel_async(void) > { > - __mte_enable_kernel("asynchronous", SCTLR_ELx_TCF_ASYNC); > + __mte_enable_kernel("asynchronous", SCTLR_EL1_TCF_ASYNC); > > /* > * MTE async mode is set system wide by the first PE that > @@ -144,7 +145,7 @@ void mte_enable_kernel_async(void) > void mte_enable_kernel_asymm(void) > { > if (cpus_have_cap(ARM64_MTE_ASYMM)) { > - __mte_enable_kernel("asymmetric", SCTLR_ELx_TCF_ASYMM); > + __mte_enable_kernel("asymmetric", SCTLR_EL1_TCF_ASYMM); > > /* > * MTE asymm mode behaves as async mode for store > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index 77341b160aca..5e280cc566ca 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -335,7 +335,8 @@ static void do_tag_recovery(unsigned long addr, unsigned int esr, > * It will be done lazily on the other CPUs when they will hit a > * tag fault. > */ > - sysreg_clear_set(sctlr_el1, SCTLR_ELx_TCF_MASK, SCTLR_ELx_TCF_NONE); > + sysreg_clear_set(sctlr_el1, SCTLR_EL1_TCF_MASK, > + SYS_FIELD_PREP_ENUM(SCTLR_EL1, TCF, NONE)); > isb(); > } > > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel