linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1
Date: Wed, 4 May 2022 14:35:25 +0100	[thread overview]
Message-ID: <YnKBHRvu9X2HqYKt@FVFF77S0Q05N> (raw)
In-Reply-To: <20220503170233.507788-6-broonie@kernel.org>

On Tue, May 03, 2022 at 06:02:26PM +0100, Mark Brown wrote:
> In older revisions of the architecture SCTLR_EL1 contained several RES1
> fields but in DDI0487H.a these now all have assigned functions. In
> preparation for automatically generating sysreg.h provide explicit
> definitions for all these bits and use them in the INIT_SCTLR_EL1_ macros
> where _RES1 was previously used.
> 
> There should be no functional change.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

AFAICT all the bits are good, and there should be no functional change:

Reviewed-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/sysreg.h | 53 ++++++++++++++++++++-------------
>  1 file changed, 32 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 7e9de3c87cd9..331e2521a81a 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -633,19 +633,24 @@
>  
>  #define SCTLR_ELx_ENIA_SHIFT	31
>  
> -#define SCTLR_ELx_ITFSB	(BIT(37))
> -#define SCTLR_ELx_ENIA	(BIT(SCTLR_ELx_ENIA_SHIFT))
> -#define SCTLR_ELx_ENIB	(BIT(30))
> -#define SCTLR_ELx_ENDA	(BIT(27))
> -#define SCTLR_ELx_EE    (BIT(25))
> -#define SCTLR_ELx_IESB	(BIT(21))
> -#define SCTLR_ELx_WXN	(BIT(19))
> -#define SCTLR_ELx_ENDB	(BIT(13))
> -#define SCTLR_ELx_I	(BIT(12))
> -#define SCTLR_ELx_SA	(BIT(3))
> -#define SCTLR_ELx_C	(BIT(2))
> -#define SCTLR_ELx_A	(BIT(1))
> -#define SCTLR_ELx_M	(BIT(0))
> +#define SCTLR_ELx_ITFSB	 (BIT(37))
> +#define SCTLR_ELx_ENIA	 (BIT(SCTLR_ELx_ENIA_SHIFT))
> +#define SCTLR_ELx_ENIB	 (BIT(30))
> +#define SCTLR_ELx_LSMAOE (BIT(29))
> +#define SCTLR_ELx_nTLSMD (BIT(28))
> +#define SCTLR_ELx_ENDA	 (BIT(27))
> +#define SCTLR_ELx_EE     (BIT(25))
> +#define SCTLR_ELx_EIS	 (BIT(22))
> +#define SCTLR_ELx_IESB	 (BIT(21))
> +#define SCTLR_ELx_TSCXT	 (BIT(20))
> +#define SCTLR_ELx_WXN	 (BIT(19))
> +#define SCTLR_ELx_ENDB	 (BIT(13))
> +#define SCTLR_ELx_I	 (BIT(12))
> +#define SCTLR_ELx_EOS	 (BIT(11))
> +#define SCTLR_ELx_SA	 (BIT(3))
> +#define SCTLR_ELx_C	 (BIT(2))
> +#define SCTLR_ELx_A	 (BIT(1))
> +#define SCTLR_ELx_M	 (BIT(0))
>  
>  /* SCTLR_EL2 specific flags. */
>  #define SCTLR_EL2_RES1	((BIT(4))  | (BIT(5))  | (BIT(11)) | (BIT(16)) | \
> @@ -686,22 +691,24 @@
>  
>  #define SCTLR_EL1_BT1		(BIT(36))
>  #define SCTLR_EL1_BT0		(BIT(35))
> +#define SCTLR_EL1_LSMAOE	(BIT(29))
> +#define SCTLR_EL1_nTLSMD	(BIT(28))
>  #define SCTLR_EL1_UCI		(BIT(26))
>  #define SCTLR_EL1_E0E		(BIT(24))
>  #define SCTLR_EL1_SPAN		(BIT(23))
> +#define SCTLR_EL1_EIS		(BIT(22))
> +#define SCTLR_EL1_TSCXT		(BIT(20))
>  #define SCTLR_EL1_nTWE		(BIT(18))
>  #define SCTLR_EL1_nTWI		(BIT(16))
>  #define SCTLR_EL1_UCT		(BIT(15))
>  #define SCTLR_EL1_DZE		(BIT(14))
> +#define SCTLR_EL1_EOS		(BIT(11))
>  #define SCTLR_EL1_UMA		(BIT(9))
>  #define SCTLR_EL1_SED		(BIT(8))
>  #define SCTLR_EL1_ITD		(BIT(7))
>  #define SCTLR_EL1_CP15BEN	(BIT(5))
>  #define SCTLR_EL1_SA0		(BIT(4))
>  
> -#define SCTLR_EL1_RES1	((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
> -			 (BIT(29)))
> -
>  #ifdef CONFIG_CPU_BIG_ENDIAN
>  #define ENDIAN_SET_EL1		(SCTLR_EL1_E0E | SCTLR_ELx_EE)
>  #else
> @@ -709,13 +716,17 @@
>  #endif
>  
>  #define INIT_SCTLR_EL1_MMU_OFF \
> -	(ENDIAN_SET_EL1 | SCTLR_EL1_RES1)
> +	(ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \
> +	 SCTLR_EL1_EIS  | SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
>  
>  #define INIT_SCTLR_EL1_MMU_ON \
> -	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
> -	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
> -	 SCTLR_EL1_nTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
> -	 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
> +	(SCTLR_ELx_M      | SCTLR_ELx_C      | SCTLR_ELx_SA    | \
> +	 SCTLR_EL1_SA0    | SCTLR_EL1_SED    | SCTLR_ELx_I     | \
> +	 SCTLR_EL1_DZE    | SCTLR_EL1_UCT    | SCTLR_EL1_nTWE  | \
> +	 SCTLR_ELx_IESB   | SCTLR_EL1_SPAN   | SCTLR_ELx_ITFSB | \
> +	 ENDIAN_SET_EL1   | SCTLR_EL1_UCI    | SCTLR_EL1_EPAN  | \
> +	 SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS   | \
> +	 SCTLR_EL1_TSCXT  | SCTLR_EL1_EOS)
>  
>  /* MAIR_ELx memory attributes (used by Linux) */
>  #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
> -- 
> 2.30.2
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-05-04 13:36 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 17:02 [PATCH v6 00/12] arm64: Automatic system register definition generation Mark Brown
2022-05-03 17:02 ` [PATCH v6 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
2022-05-03 17:02 ` [PATCH v6 02/12] arm64/mte: Make TCF0 naming and field values more standard Mark Brown
2022-05-03 17:02 ` [PATCH v6 03/12] arm64/mte: Make TCF field values and naming " Mark Brown
2022-05-04 13:26   ` Mark Rutland
2022-05-03 17:02 ` [PATCH v6 04/12] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-05-03 17:02 ` [PATCH v6 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 Mark Brown
2022-05-04 13:35   ` Mark Rutland [this message]
2022-05-03 17:02 ` [PATCH v6 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Mark Brown
2022-05-03 17:02 ` [PATCH v6 07/12] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-05-03 17:02 ` [PATCH v6 08/12] arm64: Add sysreg header generation scripting Mark Brown
2022-05-03 17:02 ` [PATCH v6 09/12] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-05-03 17:02 ` [PATCH v6 10/12] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-05-03 17:02 ` [PATCH v6 11/12] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-05-03 17:02 ` [PATCH v6 12/12] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-05-04 16:32   ` Mark Rutland
2022-05-04 16:40     ` Mark Brown
2022-05-04 17:56       ` Catalin Marinas
2022-05-04 16:17 ` [PATCH v6 00/12] arm64: Automatic system register definition generation Catalin Marinas
2022-05-04 19:58 ` Catalin Marinas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YnKBHRvu9X2HqYKt@FVFF77S0Q05N \
    --to=mark.rutland@arm.com \
    --cc=broonie@kernel.org \
    --cc=catalin.marinas@arm.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=maz@kernel.org \
    --cc=suzuki.poulose@arm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).