From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 640C9C433EF for ; Fri, 20 May 2022 15:21:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/2fEhXAPbe5vIxAMnXOKkKN4q3XP4a0UhuhGsMWQfj8=; b=BB2eWGHMlhf3UR b1OxWpaKZeKfbv9RdDfLhkXhTZR2H0v0YngvVkHlI6wrnotTUoqW1ulvJM71W1g9KPAApqtf4FfhQ rrO+jmRusvs4CDE4VoV3qjJX+meAdhHTIuy/NHVzo+XnqRsYIfG0vyYbuK6yQwVaEFnnEfpe16YuV H5XmKMUUbTIQwie9Q9BaR5Z9O6ijmslY0P3wRYlrciUe3mT9/Fc72QY/ELop9l5qM9j7XWz6RchzC AJDjArOtpicFBngp9zfHsLzIEVLjQ7FhoCeSxld01VjzPVMwUl9YPCkh7HrzB884be8ZkSz2txQ/O RxeWv8oW9FJaT4U9rB/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4Qc-00D8cH-Ir; Fri, 20 May 2022 15:20:34 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4QZ-00D8bQ-GB for linux-arm-kernel@lists.infradead.org; Fri, 20 May 2022 15:20:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2976F1477; Fri, 20 May 2022 08:20:30 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.7.188]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 726833F73D; Fri, 20 May 2022 08:20:29 -0700 (PDT) Date: Fri, 20 May 2022 16:20:25 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Message-ID: References: <20220517182219.2171814-1-broonie@kernel.org> <20220517182219.2171814-7-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220517182219.2171814-7-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220520_082031_620554_171B7106 X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote: > Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no > functional change. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 1 - > arch/arm64/tools/sysreg | 15 +++++++++++++++ > 2 files changed, 15 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 6240149f9818..c77e2310d189 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -461,7 +461,6 @@ > #define SMIDR_EL1_SMPS_SHIFT 15 > #define SMIDR_EL1_AFFINITY_SHIFT 0 > > -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) > #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) > > #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 47c4c45d5dc3..3971e1fb6af4 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -277,6 +277,21 @@ Field 3:1 Level > Field 0 InD > EndSysreg > > +Sysreg CTR_EL0 3 3 0 0 1 > +Res0 63:38 > +Field 37:32 TminLine > +Res1 31 > +Res0 30 > +Field 29 DIC > +Field 28 IDC > +Field 27:24 CWG > +Field 23:20 ERG > +Field 19:16 DminLine > +Field 15:14 L1Ip > +Res0 13:4 > +Field 3:0 IminLine > +EndSysreg The values all look right to me. The L1Ip field is an enumeration where: * 0b00 means VPIPT * 0b01 means AIVIVT // reserved in ARMv8 * 0b10 means VIPT * 0b11 means PIPT So I reckon we want to describe that as: Enum 15:14 L1Ip 0b00 VPIPT 0b01 AIVIVT # or RESERVED 0b10 VIPT 0b11 PIPT EndEnum We have some existing definitions that could be removed (and their users converted over): | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT 0 | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED 1 | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT 2 | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT 3 Thanks, Mark. > + > Sysreg SVCR 3 3 4 2 2 > Res0 63:2 > Field 1 ZA > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel