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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4Z8-00DCod-WC; Fri, 20 May 2022 15:29:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4Z4-00DCmN-Rs for linux-arm-kernel@lists.infradead.org; Fri, 20 May 2022 15:29:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51CC81477; Fri, 20 May 2022 08:29:17 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.7.188]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 70C393F73D; Fri, 20 May 2022 08:29:16 -0700 (PDT) Date: Fri, 20 May 2022 16:29:12 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v1 6/9] arm64/sysreg: Generate definitions for CTR_EL0 Message-ID: References: <20220517182219.2171814-1-broonie@kernel.org> <20220517182219.2171814-7-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220520_082919_039957_2826E74D X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 20, 2022 at 04:20:25PM +0100, Mark Rutland wrote: > On Tue, May 17, 2022 at 07:22:16PM +0100, Mark Brown wrote: > > Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no > > functional change. > > > > Signed-off-by: Mark Brown > > --- > > arch/arm64/include/asm/sysreg.h | 1 - > > arch/arm64/tools/sysreg | 15 +++++++++++++++ > > 2 files changed, 15 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index 6240149f9818..c77e2310d189 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -461,7 +461,6 @@ > > #define SMIDR_EL1_SMPS_SHIFT 15 > > #define SMIDR_EL1_AFFINITY_SHIFT 0 > > > > -#define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) > > #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) > > > > #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > > index 47c4c45d5dc3..3971e1fb6af4 100644 > > --- a/arch/arm64/tools/sysreg > > +++ b/arch/arm64/tools/sysreg > > @@ -277,6 +277,21 @@ Field 3:1 Level > > Field 0 InD > > EndSysreg > > > > +Sysreg CTR_EL0 3 3 0 0 1 > > +Res0 63:38 > > +Field 37:32 TminLine > > +Res1 31 > > +Res0 30 > > +Field 29 DIC > > +Field 28 IDC > > +Field 27:24 CWG > > +Field 23:20 ERG > > +Field 19:16 DminLine > > +Field 15:14 L1Ip > > +Res0 13:4 > > +Field 3:0 IminLine > > +EndSysreg > > The values all look right to me. > > The L1Ip field is an enumeration where: > > * 0b00 means VPIPT > * 0b01 means AIVIVT // reserved in ARMv8 > * 0b10 means VIPT > * 0b11 means PIPT > > So I reckon we want to describe that as: > > Enum 15:14 L1Ip > 0b00 VPIPT > 0b01 AIVIVT # or RESERVED > 0b10 VIPT > 0b11 PIPT > EndEnum > > We have some existing definitions that could be removed (and their users > converted over): > > | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VPIPT 0 > | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_RESERVED 1 > | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_VIPT 2 > | arch/arm64/include/asm/cache.h:#define ICACHE_POLICY_PIPT 3 Likewise there are CTR_* definitions that should be converted over along with their users: arch/arm64/include/asm/cache.h:#define CTR_L1IP_MASK 3 arch/arm64/include/asm/cache.h:#define CTR_DMINLINE_SHIFT 16 arch/arm64/include/asm/cache.h:#define CTR_IMINLINE_SHIFT 0 arch/arm64/include/asm/cache.h:#define CTR_IMINLINE_MASK 0xf arch/arm64/include/asm/cache.h:#define CTR_ERG_SHIFT 20 arch/arm64/include/asm/cache.h:#define CTR_CWG_SHIFT 24 arch/arm64/include/asm/cache.h:#define CTR_CWG_MASK 15 arch/arm64/include/asm/cache.h:#define CTR_IDC_SHIFT 28 arch/arm64/include/asm/cache.h:#define CTR_DIC_SHIFT 29 arch/arm64/include/asm/cache.h:#define CTR_CACHE_MINLINE_MASK \ arch/arm64/include/asm/cache.h: (0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT) arch/arm64/include/asm/cache.h:#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel