From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24256C43334 for ; Fri, 17 Jun 2022 19:42:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BLskjf/yK8BXqT/g5cTBS3JET8V2nHs0SRdH1iKGFhM=; b=y4aUg+B2dXtm7L 7Gk/6wS9QHv4UXsHxKUgPqCv7RXsL9QlzqPJJzlqRAplOaJis3v3kOo81OteXLfQSJMwfKyvEOGSt An9RYUxPxmqkA4gPpdveUGwlJDO+7FjjiRmSN3CqK8/NAJN/2a5y1OtA4dS0LPnogBNr5o9uVilMm HJ6v/WfFI7Y5FaGY8AuCelzUTKhd6bIsmL/LmuwInepWu95qO/w5QV64Y2qGggaMTzgIyNuyTSdsg xuOVquFIZzvsDZZpoScy7GBRdLy6ONVLZ1z7rcQXmmsoNlQgX//GQZiFS1FI1+sT6+lgWXI7MRPED pYR3V87t0cT0+H6aZjIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o2HqV-008pdT-B9; Fri, 17 Jun 2022 19:41:31 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o2HqP-008pa7-Na for linux-arm-kernel@bombadil.infradead.org; Fri, 17 Jun 2022 19:41:25 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=NguTtxmReR8PZgsdiEJ1iaB38S81bma6uJptJHOnrno=; b=l5Kg+QgNoVC74Woptdnyz0IkEt x0idqUdY2rKrNFDDXfGltGuvpmvE0XeuKIOGK5pb/tdv4kXD+8Qa86MxOOY7JnSG1BgNDRrz540Ms w4m5amRFGiEFWfJwCy/fLTvElR+tXoejvC3zLnivPGao0maRgGqZgxbAnmegcNeI5o4370o1jLfhm ceeMmMnrCVjpyB2wXGktuX8bGuSYnEnywOrXc3Ro14oHEhBG3WaAVoWrwJdPMwOu8Q+MW3wABff4P F9qcZWFDJCTvgFccpazzanHxH/6+NLIImQfnrxh4sRAp2dEDvP6XELwTxt7RAIDlFcZk+RBXlZPi5 epeCJ3kw==; Received: from [187.19.239.237] (helo=quaco.ghostprotocols.net) by desiato.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1o2HqL-008lU3-Ah; Fri, 17 Jun 2022 19:41:21 +0000 Received: by quaco.ghostprotocols.net (Postfix, from userid 1000) id AF3274096F; Fri, 17 Jun 2022 16:41:17 -0300 (-03) Date: Fri, 17 Jun 2022 16:41:17 -0300 From: Arnaldo Carvalho de Melo To: Ali Saidi Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org, german.gomez@arm.com, leo.yan@linaro.org, benh@kernel.crashing.org, Nick.Forrington@arm.com, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org Subject: Re: [PATCH v9 4/5] perf arm-spe: Don't set data source if it's not a memory operation Message-ID: References: <20220517020326.18580-1-alisaidi@amazon.com> <20220517020326.18580-5-alisaidi@amazon.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220517020326.18580-5-alisaidi@amazon.com> X-Url: http://acmel.wordpress.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Em Tue, May 17, 2022 at 02:03:25AM +0000, Ali Saidi escreveu: > From: Leo Yan > > Except memory load and store operations, Arm SPE records also can > support other operation types, bug when set the data source field the > current code assumes a record is a either load operation or store > operation, this leads to wrongly synthesize memory samples. > > This patch strictly checks the record operation type, it only sets data > source only for the operation types ARM_SPE_LD and ARM_SPE_ST, > otherwise, returns zero for data source. Therefore, we can synthesize > memory samples only when data source is a non-zero value, the function > arm_spe__is_memory_event() is useless and removed. Thanks, applied. - Arnaldo > Fixes: e55ed3423c1b ("perf arm-spe: Synthesize memory event") > Signed-off-by: Leo Yan > Reviewed-by: Ali Saidi > Tested-by: Ali Saidi > Reviewed-by: German Gomez > --- > tools/perf/util/arm-spe.c | 22 ++++++++-------------- > 1 file changed, 8 insertions(+), 14 deletions(-) > > diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c > index d2b64e3f588b..e032efc03274 100644 > --- a/tools/perf/util/arm-spe.c > +++ b/tools/perf/util/arm-spe.c > @@ -387,26 +387,16 @@ static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq, > return arm_spe_deliver_synth_event(spe, speq, event, &sample); > } > > -#define SPE_MEM_TYPE (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \ > - ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \ > - ARM_SPE_REMOTE_ACCESS) > - > -static bool arm_spe__is_memory_event(enum arm_spe_sample_type type) > -{ > - if (type & SPE_MEM_TYPE) > - return true; > - > - return false; > -} > - > static u64 arm_spe__synth_data_source(const struct arm_spe_record *record) > { > union perf_mem_data_src data_src = { 0 }; > > if (record->op == ARM_SPE_LD) > data_src.mem_op = PERF_MEM_OP_LOAD; > - else > + else if (record->op == ARM_SPE_ST) > data_src.mem_op = PERF_MEM_OP_STORE; > + else > + return 0; > > if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) { > data_src.mem_lvl = PERF_MEM_LVL_L3; > @@ -510,7 +500,11 @@ static int arm_spe_sample(struct arm_spe_queue *speq) > return err; > } > > - if (spe->sample_memory && arm_spe__is_memory_event(record->type)) { > + /* > + * When data_src is zero it means the record is not a memory operation, > + * skip to synthesize memory sample for this case. > + */ > + if (spe->sample_memory && data_src) { > err = arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); > if (err) > return err; > -- > 2.32.0 -- - Arnaldo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel