From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F1E3C433EF for ; Mon, 20 Jun 2022 15:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9/eCCg2QcofaPv+UQ5PZ6io9xl347Q8rXNtEJZ5l39Q=; b=hzSPhnRfjTF9hp eqFvoptsE4gFwg09XLGmoN5fb6R+9hLyo2wa0WNXBuWDFz9pwddO516yZrX+1s75X7AqLCIf7rnBP ivP3luQHkYIepCzixEk+Ezuq744LrJ6tfQvlfOYJn8CyI0trG7Z+owCHppAvHTVLHykphVLxJogP3 z3gMm5WvaBw32sZ69778lUvgAD7gytvrYZG9abKlN6H4nWKaF4aNPSfJn5+ElrNkwiNytkYK9LkGE FYMCSkLenFouiYFFmBJUtLXEJ46bLd4tfMq2Jl54+qA5E6VVpHmISzgS1u2AbC8FiHli3L0VnXvzP Dwbioax3cue9P1qF7UlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3Jm7-001LvZ-M4; Mon, 20 Jun 2022 15:57:15 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3Jm3-001LuF-8R for linux-arm-kernel@lists.infradead.org; Mon, 20 Jun 2022 15:57:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A6861B81240; Mon, 20 Jun 2022 15:57:09 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49BCEC3411B; Mon, 20 Jun 2022 15:57:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655740629; bh=hhtTUOQfB7NyL9lep8rwJsK7rGNq5Oan7in7ywvgSxs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ebSsNJHidxvB9LEuWx06Hl9kjrsuupGEiX31v87y0QcuyCsKx5hze2Vwee2zc1Qn1 s/JQ35oQGP1YJSnddrNF29JtO2dKjCiW/atw/JgMmWLKf+T+Gofm3iCiiM0p+oGFZQ H/pQXjEPD1+z9QiWltPGR6O1vtB8Fu3A8EHwOOJO2xTrhUfcxRCizM+lbqOlQHsqku qxPqzWRQ+K2hHgEW57QWZKWgaUTe0VuYQ8ZD5MHEbIXC9d7rJkQPm//CGT1NRqfkFf XtnDbS9DVcaVUmepSiwKMUq8TxDdaSPsFNQyZ0cBs2alkCj8qNlYUstZubVGEu52UI fwwYuxkZPSYhA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1o3Jlx-0003MR-7t; Mon, 20 Jun 2022 17:57:05 +0200 Date: Mon, 20 Jun 2022 17:57:05 +0200 From: Johan Hovold To: Baruch Siach Cc: Andy Gross , Bjorn Andersson , Stanimir Varbanov , Selvam Sathappan Periakaruppan , Selvam Sathappan Periakaruppan , Baruch Siach , Kathiravan T , Bjorn Helgaas , Rob Herring , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , Bryan O'Donoghue , Pali =?utf-8?B?Um9ow6Fy?= , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v7 3/3] PCI: qcom: Add IPQ60xx support Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_085711_620613_F3E1FC5B X-CRM114-Status: GOOD ( 24.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jun 12, 2022 at 01:18:35PM +0300, Baruch Siach wrote: > From: Selvam Sathappan Periakaruppan > > IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that > platform. > > The code is based on downstream[1] Codeaurora kernel v5.4 (branch > win.linuxopenwrt.2.0). > > Split out the DBI registers access part from .init into .post_init. DBI > registers are only accessible after phy_power_on(). > > [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ > > Signed-off-by: Selvam Sathappan Periakaruppan > Signed-off-by: Baruch Siach > --- > +static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) > +{ > + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; > + > + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); Assert reset as you do in the init error path? > +} > + > +static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) > +{ > + struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; > + struct device *dev = pcie->pci->dev; > + int ret; > + > + ret = reset_control_assert(res->rst); > + if (ret) { > + dev_err(dev, "reset assert failed (%d)\n", ret); > + return ret; > + } > + > + /* > + * Delay periods before and after reset deassert are working values > + * from downstream Codeaurora kernel > + */ > + usleep_range(2000, 2500); > + > + ret = reset_control_deassert(res->rst); > + if (ret) { > + dev_err(dev, "reset deassert failed (%d)\n", ret); > + return ret; > + } > + > + usleep_range(2000, 2500); > + > + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); > + if (ret) > + goto err_reset; > + > + return 0; > + > +err_reset: > + reset_control_assert(res->rst); > + > + return ret; > +} > + > +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) > +{ > + struct dw_pcie *pci = pcie->pci; > + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + u32 val; > + int i; > + > + writel(SLV_ADDR_SPACE_SZ, > + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); > + > + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); > + val &= ~BIT(0); > + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); > + > + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); > + > + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); > + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, > + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); > + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS > + | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, I noticed that some of this probably has been copied from from qcom_pcie_init_2_3_3(), but please move the | operator to the previous line. > + pci->dbi_base + GEN3_RELATED_OFF); > + > + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS > + | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | Same here. > + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, > + pcie->parf + PCIE20_PARF_SYS_CTRL); > + > + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); > + > + dw_pcie_dbi_ro_wr_en(pci); > + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); > + > + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); > + val &= ~PCI_EXP_LNKCAP_ASPMS; > + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); > + > + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + > + PCI_EXP_DEVCTL2); > + > + for (i = 0; i < 256; i++) > + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N > + + (4 * i)); And here for +, but you should probably just remove the line break (you can go up to 100 chars if it makes the code more readable). Please drop the 0x prefix too. > + > + return 0; > +} Johan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel