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* [PATCH] arm64:kernel:Fix typo in comment
@ 2022-06-22  9:19 Jilin Yuan
  2022-06-22  9:23 ` Marc Zyngier
  2022-06-22 10:07 ` Russell King (Oracle)
  0 siblings, 2 replies; 5+ messages in thread
From: Jilin Yuan @ 2022-06-22  9:19 UTC (permalink / raw)
  To: catalin.marinas, will
  Cc: maz, joey.gouly, broonie, linux-arm-kernel, linux-kernel,
	Jilin Yuan

Delete the redundant word 'ARM'.

Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
---
 arch/arm64/kernel/cpuinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 8eff0a34ffd4..bf61222c2c69 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -241,7 +241,7 @@ static struct kobj_type cpuregs_kobj_type = {
 };
 
 /*
- * The ARM ARM uses the phrase "32-bit register" to describe a register
+ * The ARM uses the phrase "32-bit register" to describe a register
  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
  * no statement is made as to whether the upper 32 bits will or will not
  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
-- 
2.36.1


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^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH] arm64:kernel:Fix typo in comment
@ 2022-06-22  9:14 Jilin Yuan
  2022-06-22 10:40 ` Mark Brown
  0 siblings, 1 reply; 5+ messages in thread
From: Jilin Yuan @ 2022-06-22  9:14 UTC (permalink / raw)
  To: catalin.marinas, will
  Cc: broonie, maz, bigeasy, geert+renesas, linux-arm-kernel,
	linux-kernel, Jilin Yuan

Delete the redundant word 'in'.

Signed-off-by: Jilin Yuan <yuanjilin@cdjrlc.com>
---
 arch/arm64/kernel/fpsimd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index 819979398127..f1d476fa50a9 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -331,7 +331,7 @@ void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
  *    trapping to the kernel.
  *
  *    When stored, Z0-Z31 (incorporating Vn in bits[127:0] or the
- *    corresponding Zn), P0-P15 and FFR are encoded in in
+ *    corresponding Zn), P0-P15 and FFR are encoded in
  *    task->thread.sve_state, formatted appropriately for vector
  *    length task->thread.sve_vl or, if SVCR.SM is set,
  *    task->thread.sme_vl.
-- 
2.36.1


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^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2022-06-22 10:41 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2022-06-22  9:19 [PATCH] arm64:kernel:Fix typo in comment Jilin Yuan
2022-06-22  9:23 ` Marc Zyngier
2022-06-22 10:07 ` Russell King (Oracle)
  -- strict thread matches above, loose matches on Subject: below --
2022-06-22  9:14 Jilin Yuan
2022-06-22 10:40 ` Mark Brown

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