From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9DB4C433EF for ; Sun, 26 Jun 2022 09:38:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=kpthwL90EKbH1GcsmQp3H++ztCzWRS9y9hidsUBCu5s=; b=W3LZevY3wHQHDG DC986oOnN7F+ufccYgNNO5GCXAnnF/uUWwghxN0Zq4Edk8bKz1Wr8ROQxBGs4g/gXvUfTziCkiIak IJdyFJ4BHh34ikzcxKiaSCZasFqtxE3W4wSGnlOWuBskTVq3Vd6xafo/eldCpG8IrNLm0Dw7e4GCF l4VJ1+NN/CN5F0W7CLq/6YIdHOPKri24HKogufHORE7pLLQELbPKWj2PVtN+28wRTrBsZRRZtmMZi mnv0aV9kZn7TZ9LzAKHwp8kroknLituaI7OZbbV1BFd9woaa3K5Nqub5QYr+5roBCKVQCl93YpbLq nvM5fMOEtdHA6xXVmK3Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5Ohs-00Avyj-VO; Sun, 26 Jun 2022 09:37:29 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5Ohp-00AvxS-5Z for linux-arm-kernel@lists.infradead.org; Sun, 26 Jun 2022 09:37:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B918023A; Sun, 26 Jun 2022 02:37:24 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.71.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2EC2C3F792; Sun, 26 Jun 2022 02:37:23 -0700 (PDT) Date: Sun, 26 Jun 2022 10:37:20 +0100 From: Mark Rutland To: Ard Biesheuvel Cc: linux-arm-kernel@lists.infradead.org, Marc Zyngier , Will Deacon , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual Subject: Re: [PATCH v5 04/21] arm64: head: drop idmap_ptrs_per_pgd Message-ID: References: <20220624150651.1358849-1-ardb@kernel.org> <20220624150651.1358849-5-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220624150651.1358849-5-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220626_023725_295672_7899876C X-CRM114-Status: GOOD ( 20.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 24, 2022 at 05:06:34PM +0200, Ard Biesheuvel wrote: > The assignment of idmap_ptrs_per_pgd lacks any cache invalidation, even > though it is updated with the MMU and caches disabled. However, we never > bother to read the value again except in the very next instruction, and > so we can just drop the variable entirely. > > Signed-off-by: Ard Biesheuvel > Reviewed-by: Anshuman Khandual Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/mmu_context.h | 1 - > arch/arm64/kernel/head.S | 7 +++---- > arch/arm64/mm/mmu.c | 1 - > 3 files changed, 3 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h > index 6ac0086ebb1a..7b387c3b312a 100644 > --- a/arch/arm64/include/asm/mmu_context.h > +++ b/arch/arm64/include/asm/mmu_context.h > @@ -61,7 +61,6 @@ static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm) > * physical memory, in which case it will be smaller. > */ > extern int idmap_t0sz; > -extern u64 idmap_ptrs_per_pgd; > > /* > * Ensure TCR.T0SZ is set to the provided value. > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index 7f361bc72d12..53126a35d73c 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -300,6 +300,7 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > * range in that case, and configure an additional translation level > * if needed. > */ > + mov x4, #PTRS_PER_PGD > idmap_get_t0sz x5 > cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? > b.ge 1f // .. then skip VA range extension > @@ -319,18 +320,16 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > #error "Mismatch between VA_BITS and page size/number of translation levels" > #endif > > - mov x4, EXTRA_PTRS > - create_table_entry x0, x3, EXTRA_SHIFT, x4, x5, x6 > + mov x2, EXTRA_PTRS > + create_table_entry x0, x3, EXTRA_SHIFT, x2, x5, x6 > #else > /* > * If VA_BITS == 48, we don't have to configure an additional > * translation level, but the top-level table has more entries. > */ > mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) > - str_l x4, idmap_ptrs_per_pgd, x5 > #endif > 1: > - ldr_l x4, idmap_ptrs_per_pgd > adr_l x6, __idmap_text_end // __pa(__idmap_text_end) > > map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 > diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c > index f875c4954e22..3be0e9f69406 100644 > --- a/arch/arm64/mm/mmu.c > +++ b/arch/arm64/mm/mmu.c > @@ -44,7 +44,6 @@ > #define NO_EXEC_MAPPINGS BIT(2) /* assumes FEAT_HPDS is not used */ > > int idmap_t0sz __ro_after_init; > -u64 idmap_ptrs_per_pgd = PTRS_PER_PGD; > > #if VA_BITS > 48 > u64 vabits_actual __ro_after_init = VA_BITS_MIN; > -- > 2.35.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel