From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83496C43334 for ; Sun, 26 Jun 2022 10:08:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d1ACQGhIwBKhvEtgYivGD+SnEoknjiuNxIe27jtUdK4=; b=fv0gekyeibFSOy o9DlOE6gAQk6ttp2KGK40h8VP/8dHKEe02FMxaJENoc5JCMRqiZLJzMg8oPdZIOIjo3/jfHu6r6VQ JBUaGjTKAZpKJkNwZCPBTuEjrwypuqJGLb9lWJtNQNLAfd20vqd8PrOOAXveWO+Io58Gr33G4+nAe pOgWeiOUTxKuETUYWiedNL/Nl4FwYeXvLjF2ZmoK9o96bE5z26W7d2ZWpf5byJe7hbI1YteUbLjwy VoJH87ZuivL4wC9/hTq2g5tFnzoGS4+le6t6FmgS0hRiUNpP6f/YLiuXwpnpyHg7/H+VeOyAjC3X1 7I0jwB7jiSIL2OBD25oQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5PB3-00B50O-L1; Sun, 26 Jun 2022 10:07:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5PAz-00B4y9-H1 for linux-arm-kernel@lists.infradead.org; Sun, 26 Jun 2022 10:07:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A339723A; Sun, 26 Jun 2022 03:07:27 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.71.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E3DE03F534; Sun, 26 Jun 2022 03:07:24 -0700 (PDT) Date: Sun, 26 Jun 2022 11:07:20 +0100 From: Mark Rutland To: Ard Biesheuvel Cc: linux-arm-kernel@lists.infradead.org, Marc Zyngier , Will Deacon , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual Subject: Re: [PATCH v5 05/21] arm64: head: simplify page table mapping macros (slightly) Message-ID: References: <20220624150651.1358849-1-ardb@kernel.org> <20220624150651.1358849-6-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220624150651.1358849-6-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220626_030733_717592_8C51D8A4 X-CRM114-Status: GOOD ( 28.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 24, 2022 at 05:06:35PM +0200, Ard Biesheuvel wrote: > Simplify the macros in head.S that are used to set up the early page > tables, by switching to immediates for the number of bits that are > interpreted as the table index at each level. This makes it much > easier to infer from the instruction stream what is going on, and > reduces the number of instructions emitted substantially. Nice! > Note that the extended ID map for cases where no additional level needs > to be configured now uses a compile time size as well, which means that > we interpret up to 10 bits as the table index at the root level (for > 52-bit physical addressing), without taking into account whether or not > this is supported on the current system. However, those bits can only > be set if we are executing the image from an address that exceeds the > 48-bit PA range, and are guaranteed to be cleared otherwise, and given > that we are dealing with a mapping in the lower TTBR0 range of the > address space, the result is therefore the same as if we'd mask off only > 6 bits. > > Signed-off-by: Ard Biesheuvel Aside from one trivial comment below, this looks good to me, so either way: Acked-by: Mark Rutland > --- > arch/arm64/kernel/head.S | 55 ++++++++------------ > 1 file changed, 22 insertions(+), 33 deletions(-) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index 53126a35d73c..9fdde2f9cc0f 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -179,31 +179,20 @@ SYM_CODE_END(preserve_boot_args) > * vstart: virtual address of start of range > * vend: virtual address of end of range - we map [vstart, vend] > * shift: shift used to transform virtual address into index > - * ptrs: number of entries in page table > + * order: #imm 2log(number of entries in page table) > * istart: index in table corresponding to vstart > * iend: index in table corresponding to vend > * count: On entry: how many extra entries were required in previous level, scales > * our end index. > * On exit: returns how many extra entries required for next page table level > * > - * Preserves: vstart, vend, shift, ptrs > + * Preserves: vstart, vend > * Returns: istart, iend, count > */ > - .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count > - lsr \iend, \vend, \shift > - mov \istart, \ptrs > - sub \istart, \istart, #1 > - and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1) > - mov \istart, \ptrs > - mul \istart, \istart, \count > - add \iend, \iend, \istart // iend += count * ptrs > - // our entries span multiple tables > - > - lsr \istart, \vstart, \shift > - mov \count, \ptrs > - sub \count, \count, #1 > - and \istart, \istart, \count > - > + .macro compute_indices, vstart, vend, shift, order, istart, iend, count > + ubfx \istart, \vstart, \shift, \order > + ubfx \iend, \vend, \shift, \order > + add \iend, \iend, \count, lsl \order > sub \count, \iend, \istart > .endm > > @@ -218,38 +207,39 @@ SYM_CODE_END(preserve_boot_args) > * vend: virtual address of end of range - we map [vstart, vend - 1] > * flags: flags to use to map last level entries > * phys: physical address corresponding to vstart - physical memory is contiguous > - * pgds: the number of pgd entries > + * order: #imm 2log(number of entries in PGD table) For clarity, perhaps: s/2log/ilog2/ ? The latter is used much more commonly throughot the kernel. > * > * Temporaries: istart, iend, tmp, count, sv - these need to be different registers > * Preserves: vstart, flags > * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv > */ > - .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv > + .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, order, istart, iend, tmp, count, sv > sub \vend, \vend, #1 > add \rtbl, \tbl, #PAGE_SIZE > - mov \sv, \rtbl > mov \count, #0 > - compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count > + > + compute_indices \vstart, \vend, #PGDIR_SHIFT, #\order, \istart, \iend, \count > + mov \sv, \rtbl > populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp > mov \tbl, \sv > - mov \sv, \rtbl FWIW, moving the temporary save of (r)tbl immediately around populate_entries is *much* clearer! Mark. > > #if SWAPPER_PGTABLE_LEVELS > 3 > - compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count > + compute_indices \vstart, \vend, #PUD_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count > + mov \sv, \rtbl > populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp > mov \tbl, \sv > - mov \sv, \rtbl > #endif > > #if SWAPPER_PGTABLE_LEVELS > 2 > - compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count > + compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count > + mov \sv, \rtbl > populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp > mov \tbl, \sv > #endif > > - compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count > - bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1 > - populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp > + compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #(PAGE_SHIFT - 3), \istart, \iend, \count > + bic \rtbl, \phys, #SWAPPER_BLOCK_SIZE - 1 > + populate_entries \tbl, \rtbl, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp > .endm > > /* > @@ -300,12 +290,12 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > * range in that case, and configure an additional translation level > * if needed. > */ > - mov x4, #PTRS_PER_PGD > idmap_get_t0sz x5 > cmp x5, TCR_T0SZ(VA_BITS_MIN) // default T0SZ small enough? > b.ge 1f // .. then skip VA range extension > > #if (VA_BITS < 48) > +#define IDMAP_PGD_ORDER (VA_BITS - PGDIR_SHIFT) > #define EXTRA_SHIFT (PGDIR_SHIFT + PAGE_SHIFT - 3) > #define EXTRA_PTRS (1 << (PHYS_MASK_SHIFT - EXTRA_SHIFT)) > > @@ -323,16 +313,16 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > mov x2, EXTRA_PTRS > create_table_entry x0, x3, EXTRA_SHIFT, x2, x5, x6 > #else > +#define IDMAP_PGD_ORDER (PHYS_MASK_SHIFT - PGDIR_SHIFT) > /* > * If VA_BITS == 48, we don't have to configure an additional > * translation level, but the top-level table has more entries. > */ > - mov x4, #1 << (PHYS_MASK_SHIFT - PGDIR_SHIFT) > #endif > 1: > adr_l x6, __idmap_text_end // __pa(__idmap_text_end) > > - map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14 > + map_memory x0, x1, x3, x6, x7, x3, IDMAP_PGD_ORDER, x10, x11, x12, x13, x14 > > /* > * Map the kernel image (starting with PHYS_OFFSET). > @@ -340,13 +330,12 @@ SYM_FUNC_START_LOCAL(__create_page_tables) > adrp x0, init_pg_dir > mov_q x5, KIMAGE_VADDR // compile time __va(_text) > add x5, x5, x23 // add KASLR displacement > - mov x4, PTRS_PER_PGD > adrp x6, _end // runtime __pa(_end) > adrp x3, _text // runtime __pa(_text) > sub x6, x6, x3 // _end - _text > add x6, x6, x5 // runtime __va(_end) > > - map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14 > + map_memory x0, x1, x5, x6, x7, x3, (VA_BITS - PGDIR_SHIFT), x10, x11, x12, x13, x14 > > /* > * Since the page tables have been populated with non-cacheable > -- > 2.35.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel