From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 947A6C3F6B0 for ; Tue, 26 Jul 2022 13:57:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tVjNHeaLvrNiub468V+gnjVBlzPGWlAr/Njzy8dq6Wo=; b=4puVpMNmiZgszG dg7FGMZi+fLT5szH6L+xN5qFyECqmqUP0arYBe3NGn6zutyU7P5aURPjXQXne9A7XdGxQc2Nuca8o DvoTTT73Hbg5snRKXCZZtiokDHbmrx2Mldey2RrRAGjzGuT0OitoAzUrqlMTpjf7D3PiKd6Id+YKm k/+ZpP52doC4vqErbbQsoHbPYbJI6TnGfhdPdmeU1vByNokvnK0QRZVGUq4IATd6hJnroszqm45s7 8Y4YPvSiQj8/YHWEGWkmWwNt/wf35KypcmpvTFNRR9fgaaMkBUnXur7Qx0ewgilCSqhAZedsmZMb/ IsPild141Yp92OB4RBIg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oGL0h-00HXn2-EM; Tue, 26 Jul 2022 13:54:07 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oGL0M-00HXbr-94 for linux-arm-kernel@lists.infradead.org; Tue, 26 Jul 2022 13:53:47 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E7DE16159D; Tue, 26 Jul 2022 13:53:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60604C433C1; Tue, 26 Jul 2022 13:53:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1658843622; bh=Q8EDUoUoIfZ8TB6aJhkSBmIUfxX4ZXZBCvhBlkyNBC0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=lrmPROKxwKLYn+8T+AWGXjuFFwZuJlVmYnEMm5/H9JXJVhicdtk4NjdTPeNoV0v5W qx42zzf60YxTytQx+FjH7haQ1TP1ImunoAiRFWfH8+yIeeNW+GVW4rMUVdVvmJUehb CSiOGSwGg9c6PfTJzbhZTfNqPx7yEXJn1g0rLrkxHpcFzK4SKxa5gzPXS9egjdm0gr LjI+h6LmFHSeQsYRZq3Zwc7QymIii47mwS70b8VUagFJfibaNXM79J1Cgyg91KATlH NeTxpOSKhH52iyMi1cpSAQgjsQpew0+Dm8ZNXzBFMBLgN5xYb+v5ce9KIAHUc0TbZe H1yVRQazZUJMQ== Date: Tue, 26 Jul 2022 21:44:40 +0800 From: Jisheng Zhang To: Will Deacon Cc: Catalin Marinas , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: save movk instructions in mov_q when the lower 16|32 bits are all zero Message-ID: References: <20220709084830.3124-1-jszhang@kernel.org> <20220719181340.GC14526@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220719181340.GC14526@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220726_065346_454256_62E4978F X-CRM114-Status: GOOD ( 23.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 19, 2022 at 07:13:41PM +0100, Will Deacon wrote: > On Sat, Jul 09, 2022 at 04:48:30PM +0800, Jisheng Zhang wrote: > > Currently mov_q is used to move a constant into a 64-bit register, > > when the lower 16 or 32bits of the constant are all zero, the mov_q > > emits one or two useless movk instructions. If the mov_q macro is used > > in hot code path, we want to save the movk instructions as much as > > possible. For example, when CONFIG_ARM64_MTE is 'Y' and > > CONFIG_KASAN_HW_TAGS is 'N', the following code in __cpu_setup() > > routine is the pontential optimization target: > > > > /* set the TCR_EL1 bits */ > > mov_q x10, TCR_MTE_FLAGS > > > > Before the patch: > > mov x10, #0x10000000000000 > > movk x10, #0x40, lsl #32 > > movk x10, #0x0, lsl #16 > > movk x10, #0x0 > > > > After the patch: > > mov x10, #0x10000000000000 > > movk x10, #0x40, lsl #32 > > > > Signed-off-by: Jisheng Zhang > > --- > > arch/arm64/include/asm/assembler.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > > index 8c5a61aeaf8e..09f408424cae 100644 > > --- a/arch/arm64/include/asm/assembler.h > > +++ b/arch/arm64/include/asm/assembler.h > > @@ -568,9 +568,13 @@ alternative_endif > > movz \reg, :abs_g3:\val > > movk \reg, :abs_g2_nc:\val > > .endif > > + .if ((((\val) >> 16) & 0xffff) != 0) > > movk \reg, :abs_g1_nc:\val > > .endif > > + .endif > > + .if (((\val) & 0xffff) != 0) > > movk \reg, :abs_g0_nc:\val > > + .endif > > Please provide some numbers showing that this is worthwhile. > No, I have no performance numbers, but here are my opnion about this patch: the two checks doesn't add maintaince effort, its readability is good, if the two checks can save two movk instructions, it's worthwhile to add the checks. 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