From: Catalin Marinas <catalin.marinas@arm.com>
To: Conor.Dooley@microchip.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
palmer@rivosinc.com, aou@eecs.berkeley.edu, sudeep.holla@arm.com,
will@kernel.org, gregkh@linuxfoundation.org, rafael@kernel.org,
Daire.McNamara@microchip.com, niklas.cassel@wdc.com,
damien.lemoal@opensource.wdc.com, geert@linux-m68k.org,
zong.li@sifive.com, kernel@esmil.dk, hahnjo@hahnjo.de,
guoren@kernel.org, anup@brainfault.org, atishp@atishpatra.org,
heiko@sntech.de, philipp.tomsich@vrull.eu, robh@kernel.org,
maz@kernel.org, viresh.kumar@linaro.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Brice.Goglin@inria.fr
Subject: Re: [PATCH v4 1/2] arm64: topology: move store_cpu_topology() to shared code
Date: Tue, 19 Jul 2022 13:00:44 +0100 [thread overview]
Message-ID: <Ytac7G1zlq6WW4jt@arm.com> (raw)
In-Reply-To: <198b0486-29e7-9729-d137-0470e93038fa@microchip.com>
On Tue, Jul 19, 2022 at 11:51:04AM +0000, Conor.Dooley@microchip.com wrote:
> On 19/07/2022 12:41, Catalin Marinas wrote:
> > On Fri, Jul 15, 2022 at 06:51:55PM +0100, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> arm64's method of defining a default cpu topology requires only minimal
> >> changes to apply to RISC-V also. The current arm64 implementation exits
> >> early in a uniprocessor configuration by reading MPIDR & claiming that
> >> uniprocessor can rely on the default values.
> >>
> >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
> >> topology: Stop using MPIDR for topology information")', because the
> >> current code just assigns default values for multiprocessor systems.
> >>
> >> With the MPIDR references removed, store_cpu_topolgy() can be moved to
> >> the common arch_topology code.
> >>
> >> CC: stable@vger.kernel.org
> >
> > I'd quantify how far back you want this to go. IIUC based on the Fixes
> > tag in the other patch, it should stop at 5.4. If you send a pull
> > request instead and have a fixed commit id, you could add it as a
> > prerequisite on the following patch without a cc stable here.
>
> I guess a PR might be the easiest way for it anyway, so that both
> yourself and Palmer could merge it?
I guess so, a stable branch would do. Note that Will is handling the
upcoming merging window.
--
Catalin
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next prev parent reply other threads:[~2022-07-19 12:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 17:51 [PATCH v4 0/2] Fix RISC-V's arch-topology reporting Conor Dooley
2022-07-15 17:51 ` [PATCH v4 1/2] arm64: topology: move store_cpu_topology() to shared code Conor Dooley
2022-07-19 11:41 ` Catalin Marinas
2022-07-19 11:51 ` Conor.Dooley
2022-07-19 12:00 ` Catalin Marinas [this message]
2022-07-26 8:10 ` Atish Patra
2022-07-15 17:51 ` [PATCH v4 2/2] riscv: topology: fix default topology reporting Conor Dooley
2022-07-26 8:24 ` Atish Patra
2022-07-16 13:35 ` [PATCH v4 0/2] Fix RISC-V's arch-topology reporting Conor.Dooley
2022-07-23 11:22 ` Conor.Dooley
2022-07-25 9:13 ` Will Deacon
2022-07-25 9:20 ` Conor.Dooley
2022-07-26 8:12 ` Atish Patra
2022-07-26 9:14 ` Conor.Dooley
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