From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B394C04A68 for ; Wed, 27 Jul 2022 10:20:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=glWe22cZdP4gbjFridCGuc/Bp935IF+Y5LMBPD7uEmo=; b=nPsZPyFEuOtVIV KbMNXp90EfPsbdjDy4YDnSNf4DdSIUodzdolZtMY6RSL4k9idr6xzkd92iUTUopZ/T4eiJvV1felE lKW8hhaiF/CLn1iljQoUVYJFiEox5TSbyS2SGsPOB7h9EIG+fGg4Yyg2iekgEsrjKiNp0ktdczMRE lyVKZj6u1qFT6muRdIECFH3/SmXZMEI8NfBMDV7fLEjY1no0WNsufpx8M82tOeKnkVcZJpmDULdJD nPkdPEJ9CfcVvQ/eRdd1R+m8S2wfyk1MIa+mODtKiDh76FUqHTyTEMlIIYSknHEJq/Op4BDmlRieY ywBuek6T1VyYXtNu6wng==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oGe7z-00CHYz-Ll; Wed, 27 Jul 2022 10:18:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oGe7w-00CHWE-2y for linux-arm-kernel@lists.infradead.org; Wed, 27 Jul 2022 10:18:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 471BFD6E; Wed, 27 Jul 2022 03:18:50 -0700 (PDT) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD7473F70D; Wed, 27 Jul 2022 03:18:48 -0700 (PDT) Date: Wed, 27 Jul 2022 11:19:20 +0100 From: Alexandru Elisei To: Oliver Upton Cc: Will Deacon , maz@kernel.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Subject: Re: KVM/arm64: SPE: Translate VA to IPA on a stage 2 fault instead of pinning VM memory Message-ID: References: <20220419141012.GB6143@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220727_031852_246196_57B1C4DA X-CRM114-Status: GOOD ( 46.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Oliver, Thank you for the help, replies below. On Tue, Jul 26, 2022 at 10:51:21AM -0700, Oliver Upton wrote: > Hi Alex, > > On Mon, Jul 25, 2022 at 11:06:24AM +0100, Alexandru Elisei wrote: > > [...] > > > > A funkier approach might be to defer pinning of the buffer until the SPE is > > > enabled and avoid pinning all of VM memory that way, although I can't > > > immediately tell how flexible the architecture is in allowing you to cache > > > the base/limit values. > > > > I was investigating this approach, and Mark raised a concern that I think > > might be a showstopper. > > > > Let's consider this scenario: > > > > Initial conditions: guest at EL1, profiling disabled (PMBLIMITR_EL1.E = 0, > > PMBSR_EL1.S = 0, PMSCR_EL1.{E0SPE,E1SPE} = {0,0}). > > > > 1. Guest programs the buffer and enables it (PMBLIMITR_EL1.E = 1). > > 2. Guest programs SPE to enable profiling at **EL0** > > (PMSCR_EL1.{E0SPE,E1SPE} = {1,0}). > > 3. Guest changes the translation table entries for the buffer. The > > architecture allows this. > > 4. Guest does an ERET to EL0, thus enabling profiling. > > > > Since KVM cannot trap the ERET to EL0, it will be impossible for KVM to pin > > the buffer at stage 2 when profiling gets enabled at EL0. > > Not saying we necessarily should, but this is possible with FGT no? It doesn't look to me like FEAT_FGT offers any knobs to trap ERET from EL1. Unless there's no other way, I would prefer not to have the emulation of one feature depend on the presence of another feature, > > > I can see two solutions here: > > > > a. Accept the limitation (and advertise it in the documentation) that if > > someone wants to use SPE when running as a Linux guest, the kernel used by > > the guest must not change the buffer translation table entries after the > > buffer has been enabled (PMBLIMITR_EL1.E = 1). Linux already does that, so > > running a Linux guest should not be a problem. I don't know how other OSes > > do it (but I can find out). We could also phrase it that the buffer > > translation table entries can be changed after enabling the buffer, but > > only if profiling happens at EL1. But that sounds very arbitrary. > > > > b. Pin the buffer after the stage 2 DABT that SPE will report in the > > situation above. This means that there is a blackout window, but will > > happen only once after each time the guest reprograms the buffer. I don't > > know if this is acceptable. We could say that this if this blackout window > > is not acceptable, then the guest kernel shouldn't change the translation > > table entries after enabling the buffer. > > > > Or drop the approach of pinning the buffer and go back to pinning the > > entire memory of the VM. > > > > Any thoughts on this? I would very much prefer to try to pin only the > > buffer. > > Doesn't pinning the buffer also imply pinning the stage 1 tables > responsible for its translation as well? I agree that pinning the buffer See my reply [1] to a question someone asked in an earlier iteration of the pKVM series. My conclusion is that it's impossible to stop the invalidate_range_start() MMU notifiers from being invoked for pinned pages. But I believe that can be circumvented passing the enum mmu_notifier_event event field to the arm64 KVM code and use that to decide to do the unmapping or not. I am still investigating that, but it looks promising. [1] https://lore.kernel.org/all/YuEMkKY2RU%2F2KiZW@monolith.localdoman/ > is likely the best way forward as pinning the whole of guest memory is > entirely impractical. I would say it's undesirable, not impractical. Like Marc said, vfio already pins the entire guest memory with the VFIO_IOMMMU_MAP_DMA ioctl. The difference there is that the SMMU tables are unmapped via the explicit ioctl VFIO_IOMMU_UNMAP_DMA; the SMMU doesn't use the MMU notifiers to keep in sync with host's stage 1 like KVM does. > > I'm also a bit confused on how we would manage to un-pin memory on the > way out with this. The guest is free to muck with the stage 1 and could > cause the SPU to spew a bunch of stage 2 aborts if it wanted to be > annoying. One way to tackle it would be to only allow a single > root-to-target walk to be pinned by a vCPU at a time. Any time a new > stage 2 abort comes from the SPU, we un-pin the old walk and pin the new > one instead. > > Live migration also throws a wrench in this. IOW, there are still potential > sources of blackout unattributable to guest manipulation of the SPU. I have a proposal to handle [2] that, if you want to have a look. Basically, userspace tells KVM to never allow the guest to start profiling. That means a possibly huge blackout window while the guest is being migrated, but I don't see any better solutions. [2] https://lore.kernel.org/all/20211117153842.302159-35-alexandru.elisei@arm.com/ Thanks, Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel