From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD37AC19F29 for ; Thu, 28 Jul 2022 14:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iCcqDdW19IwcVXy/ezadz+j3kx4cFbi4W7YG90736jE=; b=2nxITakHOeBKGa 587Wd5gwyE4YSSd7SMuj73F2nRqmyQBSGWr7DDw8q0gUWiwGBTdaxvyKjmHN4xQNeNsMtTxm0WyRB QsnrLpV71fwwuSefuU0irN5J9YMrQy7OOpybzXOeOADVNm1Mb56oqvX31E2yv67Y8iyUnYIpXVuep TE95WmtmIVY8nbWSmaZja+8dZHxalAotm8g0A6+XeE8nCYjjkGuULt2HXeEoME8/OePbOYyBB4Cc7 GAIv8Z62d9NVeu+AeQquNN6qwZURj5G2zZ4Gk3jtxcVquLNowYqux8QFuQpHCanPMfamFdUP/e6FP C6rCWBGjnzsuPUn2mjaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oH4xq-00AKMR-MH; Thu, 28 Jul 2022 14:58:14 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oH4xm-00AKI4-Pg for linux-arm-kernel@lists.infradead.org; Thu, 28 Jul 2022 14:58:12 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id CE78CCE25DC; Thu, 28 Jul 2022 14:58:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D7C37C433D6; Thu, 28 Jul 2022 14:57:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659020280; bh=6M9eeRLOMpyd2fv8oifdFaKJnoAlGspljCnu9f2IJFk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=vBFc2PN+5phwjOZXiEV258XXch99IrfdLHkkQWzoQDxy5izyp6BpHFkat4b8DnWJX DAq1/mozFFHXc3OEAGCdZD47/rEuRSqeOhfZmFfOcf1umPuBLrYQlf97iFI+d62Xku R4sGoBNdPBtxe0eCEu6FqU+b/mLMkpSQ9VPSLzLCDRPC4veI1ujaBh+jzOog1lNryH qRYXp8ZyrRuJuMtR+gcLEP54WGMUgC1q6NHpl57UEwE2wgCvIsJhWQWAeiEX0kuyqR nrs8BDJ7fnyZr8iJ1/q6r4zYlBTBFm9XW9MV1N1n+TPuHrBJh7p/6Zvz5vtCP+hnJL Vv3dKx7IYcewA== Date: Thu, 28 Jul 2022 22:48:58 +0800 From: Jisheng Zhang To: Ard Biesheuvel Cc: Catalin Marinas , Will Deacon , Linux ARM , Linux Kernel Mailing List Subject: Re: [PATCH] arm64: save movk instructions in mov_q when the lower 16|32 bits are all zero Message-ID: References: <20220709084830.3124-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220728_075811_366574_0E8E9A6E X-CRM114-Status: GOOD ( 19.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jul 27, 2022 at 08:15:11AM -0700, Ard Biesheuvel wrote: > On Sat, 9 Jul 2022 at 01:58, Jisheng Zhang wrote: > > > > Currently mov_q is used to move a constant into a 64-bit register, > > when the lower 16 or 32bits of the constant are all zero, the mov_q > > emits one or two useless movk instructions. If the mov_q macro is used > > in hot code path, we want to save the movk instructions as much as > > possible. For example, when CONFIG_ARM64_MTE is 'Y' and > > CONFIG_KASAN_HW_TAGS is 'N', the following code in __cpu_setup() > > routine is the pontential optimization target: > > > > /* set the TCR_EL1 bits */ > > mov_q x10, TCR_MTE_FLAGS > > > > Before the patch: > > mov x10, #0x10000000000000 > > movk x10, #0x40, lsl #32 > > movk x10, #0x0, lsl #16 > > movk x10, #0x0 > > > > After the patch: > > mov x10, #0x10000000000000 > > movk x10, #0x40, lsl #32 > > > > Signed-off-by: Jisheng Zhang > > This is broken for constants that have 0xffff in the top 16 bits, as > in that case, we will emit a MOVN/MOVK/MOVK sequence, and omitting the > MOVKs will set the corresponding field to 0xffff not 0x0. Thanks so much for this hint. I think you are right about the 0xffff in top 16bits case. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel