From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 942E6C19F2C for ; Thu, 28 Jul 2022 15:27:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qmBDaS3PsH1qAPfgX3WLrBd5CiIFnDjKK0LBLiWtAxo=; b=KgL3xtI0Y9xXoU py18CtaT842BLBFwQaTMkaVhTW2C/TCJYbBmPCNM4pH0OEEgGzfYvOB5q9U/LYBZGxEKvXiriAFh7 p9nQNOCp3qNcU5JeB2Nz3AS6D2zpXMXoQulZ0jQL2G1CjxcAlMWm629AgEpStCtOmhIUnERPWsq3Q whsUpeMt2iVsUAg4GD4iqWP1WZHMKFjLWS/bO32PU66wOti+1kyA1cLX5lCrCEYpn2AiSf8GkfzYv w3zwbZO6bj8NNJevPv2IN3Q1dnbdjZPe3HtnYOdwTr2QFEakIyPOutHv4GTu+gU/0QfRhRjTlg+De Z8qhGrFvD/SYzUk8APQg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oH5PP-00AVPJ-Rb; Thu, 28 Jul 2022 15:26:43 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oH5PN-00AVOE-Lg for linux-arm-kernel@lists.infradead.org; Thu, 28 Jul 2022 15:26:42 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CF15C61B7A; Thu, 28 Jul 2022 15:26:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9827EC433C1; Thu, 28 Jul 2022 15:26:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1659022000; bh=OY1CFZWT7ad7PEe4fFSJDPEcJ11GALMZHQVGZ3Tqumo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=f9HytRqrLmomx4xvTJW+cidOARGraS/srKv4Akng2xTx86OJwLfVXVsQNcUJe/lUx FSRGeGiMnAZZEfv7CZKiUgWdyhmUTnyfQN11WTrQY0Pd2mkEWw7v2IOoNeR7ykcVU1 QxTddwr5DpEWzduPI2YTdW9uizrIMy2GXFZWpIIw7sxnhJpz05suP/6Qvkrqk7kz6p 5wcDu9SGemwnxkdCGm1RztjLoQyZ68jhQHwMMiqtS88KqDpDIOUHsIrk1z4HpFoTht rsCjPt5wg5mRIOXMgH5zQ0WZHCPK3AvzyL/+A3rjLTMR2mrAk0cR0LuasMgPYNrzMb rS9qHXl3UX4hg== Date: Thu, 28 Jul 2022 23:17:38 +0800 From: Jisheng Zhang To: Ard Biesheuvel Cc: Catalin Marinas , Will Deacon , Linux ARM , Linux Kernel Mailing List Subject: Re: [PATCH] arm64: save movk instructions in mov_q when the lower 16|32 bits are all zero Message-ID: References: <20220709084830.3124-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220728_082641_766721_FEF8C53C X-CRM114-Status: GOOD ( 23.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 28, 2022 at 10:49:02PM +0800, Jisheng Zhang wrote: > On Wed, Jul 27, 2022 at 08:15:11AM -0700, Ard Biesheuvel wrote: > > On Sat, 9 Jul 2022 at 01:58, Jisheng Zhang wrote: > > > > > > Currently mov_q is used to move a constant into a 64-bit register, > > > when the lower 16 or 32bits of the constant are all zero, the mov_q > > > emits one or two useless movk instructions. If the mov_q macro is used > > > in hot code path, we want to save the movk instructions as much as > > > possible. For example, when CONFIG_ARM64_MTE is 'Y' and > > > CONFIG_KASAN_HW_TAGS is 'N', the following code in __cpu_setup() > > > routine is the pontential optimization target: > > > > > > /* set the TCR_EL1 bits */ > > > mov_q x10, TCR_MTE_FLAGS > > > > > > Before the patch: > > > mov x10, #0x10000000000000 > > > movk x10, #0x40, lsl #32 > > > movk x10, #0x0, lsl #16 > > > movk x10, #0x0 > > > > > > After the patch: > > > mov x10, #0x10000000000000 > > > movk x10, #0x40, lsl #32 > > > > > > Signed-off-by: Jisheng Zhang > > > > This is broken for constants that have 0xffff in the top 16 bits, as > > in that case, we will emit a MOVN/MOVK/MOVK sequence, and omitting the > > MOVKs will set the corresponding field to 0xffff not 0x0. > > Thanks so much for this hint. I think you are right about the 0xffff in > top 16bits case. > the patch breaks below usage case: mov_q x0, 0xffffffff00000000 I think the reason is mov_q starts from high bits, if we change the macro to start from LSB, then that could solve the breakage. But this needs a rewrite of mov_q _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel