From: Mark Brown <broonie@kernel.org>
To: Patrice CHOTARD <patrice.chotard@foss.st.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>,
linux-spi@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, christophe.kerello@foss.st.com
Subject: Re: [PATCH v2 1/2] spi: stm32_qspi: Add transfer_one_message() spi callback
Date: Wed, 10 Aug 2022 14:23:06 +0100 [thread overview]
Message-ID: <YvOxOg0vXSGrZLfP@sirena.org.uk> (raw)
In-Reply-To: <d41e3814-3fab-18a3-7218-d5c28eaecff8@foss.st.com>
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On Wed, Aug 10, 2022 at 03:15:08PM +0200, Patrice CHOTARD wrote:
> On 8/10/22 15:06, Mark Brown wrote:
> > Do we need to add something to the DT bindings to indicate that
> > parallel-memories is valid?
> You mean in the st,stm32-qspi.yaml DT binding file ? Right i think it could be preferable to add it.
Yes. Though I'm not clear if the bindings actually want to enforce it
there, it's a device level property not a controller level one so it
might not be something where controller support gets validated.
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next prev parent reply other threads:[~2022-08-10 13:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-10 9:32 [PATCH v2 0/2] spi: stm32_qspi: use QSPI bus as 8 lines communication channel patrice.chotard
2022-08-10 9:32 ` [PATCH v2 1/2] spi: stm32_qspi: Add transfer_one_message() spi callback patrice.chotard
2022-08-10 13:06 ` Mark Brown
2022-08-10 13:15 ` Patrice CHOTARD
2022-08-10 13:23 ` Mark Brown [this message]
2022-08-10 13:31 ` Patrice CHOTARD
2022-08-10 13:40 ` Mark Brown
2022-08-10 13:52 ` Patrice CHOTARD
2022-08-10 13:57 ` Mark Brown
2022-08-10 9:32 ` [PATCH v2 2/2] ARM: dts: stm32: Create separate pinmux for qspi cs pin in stm32mp15-pinctrl.dtsi patrice.chotard
2022-08-22 16:05 ` (subset) [PATCH v2 0/2] spi: stm32_qspi: use QSPI bus as 8 lines communication channel Mark Brown
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