Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages

From: Mark Brown <broonie@kernel.org>
To: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	Da Xue <da@libre.computer>
Subject: Re: [PATCH] spi: meson-spicc: save pow2 datarate between messages
Date: Wed, 10 Aug 2022 15:31:59 +0100	[thread overview]
Message-ID: <YvPBX7zJ72RXnrpk@sirena.org.uk> (raw)
In-Reply-To: <518f22f4-1582-924c-9eaa-28ebbe53a632@baylibre.com>

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On Wed, Aug 10, 2022 at 04:01:33PM +0200, Neil Armstrong wrote:
> On 10/08/2022 14:37, Mark Brown wrote:

> > Sure, but that doesn't really address the concern - is this something
> > that the clk driver programmed or is this the driver forgetting to
> > restore a register that it programmed itself?  The commit message sounds
> > like the former which is a much bigger problem.

> It's what is programmed by the Clock Framework yes, it was designed as-is
> so the Clock Framework takes the most accurate clock path but the reset case
> wasn't taken in account.

This seems like a bad idea, we shouldn't have two different drivers
managing the same register without explicit and visible coordination
with each other, this is at best asking for trouble as you've found
here.  I've not looked in detail but I think if you want to use the
clock framework here then this driver should register a clock provider
for the clock hardware in the IP block.

How does this work with runtime PM, what happens if the clock driver
decides to change something while the device is powered down?

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