From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28EBDC00140 for ; Mon, 15 Aug 2022 14:22:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=LNWlHFlg98eTMp9di3QZbycAvWvTm5Dp2PvXNCYxqrQ=; b=HS9P148eQxRuiN dxER6zteBbT8TrVggfmYveemJjbwAX9hKNRZLpWpT5PAWjP/2hEJZ1DiROQwkfNHaPtcEsxQe/dMm 5TR1O1cY1Qx18Kc5BNddRcaSRKYV+ZaD8kmpZJPD1H/VgCbkHvXzXROGjWjywSfUOWX+Xb1k2nMda Dx/PFVvr8Vtvu9+tVbHRUe/myo972Tk4KKZGxh6agrpcMssoAIF11CQ5/1fjabPd2IovVRPfglvOp 5zm6b5kW1xs4OxBXWv2e7vm3sNI5AdDpN+yZm87nJp+syfoSgCQtm+HJ86xLrZMpGibQ4pjISiZzo o32rbhEhA4CyKTpjWZJQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNaxj-00HTiZ-Fr; Mon, 15 Aug 2022 14:21:03 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNaaE-00H9HZ-U3 for linux-arm-kernel@bombadil.infradead.org; Mon, 15 Aug 2022 13:56:53 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=8H7M++LHjLPagFvc25ZTit0lX+9Q+HaL3iQSNzDSx5I=; b=oPueY7bmQ32LIM+kvz9NC4LcWF ZD8OH1HwyTDACmg3Hu/I8PIzoB78jKBUoOqmXDNaUFoR1wBSaJcM4PR7aqexT9t14F7sUCvPSk6y/ eLCd1hYPIRpm5qbrVJAXCeEAtY2lkGYfKM9lhIFgbH0Oa7rg9altls4wuBad9FmfNICyklfd/s80Y oozevP/mlOKuoPREQj2RpimUfCeNhFUhXwpahsbOeHTDHYvErQ6nH7ob7Kyq1Ww+CsB9hIpS7VZqo pcOq0+38PWUQC7f5AQCyPgE4DftYv1nkk3gfmGIOWEYIF4K+0rsuoyOtSqB88iJWj5ohpH4Mi1eM5 g01TU4tg==; Received: from j130084.upc-j.chello.nl ([24.132.130.84] helo=worktop.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1oNaaC-005le7-Dw; Mon, 15 Aug 2022 13:56:44 +0000 Received: by worktop.programming.kicks-ass.net (Postfix, from userid 1000) id 9CB96980153; Mon, 15 Aug 2022 15:56:43 +0200 (CEST) Date: Mon, 15 Aug 2022 15:56:43 +0200 From: Peter Zijlstra To: Will Deacon Cc: Hector Martin , Linux ARM , Greg KH , jirislaby@kernel.org, Marc Zyngier , Mark Rutland , Boqun Feng , Catalin Marinas , Asahi Linux , Oliver Neukum , LKML Subject: Re: Debugging a TTY race condition on M1 (memory ordering dragons) Message-ID: References: <6c089268-4f2c-9fdf-7bcb-107b611fbc21@marcan.st> <20220815134711.GA10374@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220815134711.GA10374@willie-the-truck> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Aug 15, 2022 at 02:47:11PM +0100, Will Deacon wrote: > > Behind the scenes, the work pending flag is atomically set with > > test_and_set_bit() by queue_work_on(). That compiles down to my old > > friend LDSETAL, which I already showed [2] does not provide the > > guarantees test_and_set_bit() claims to have (== full memory barrier). > > However, I can't get that litmus test to fail on real hardware, so that > > may be a red herring as far as this bug goes. > > As I mentioned in the thread you linked to, the architecture was undergoing > review in this area. I should've followed back up, but in the end it was > tightened retrospectively to provide the behaviour you wanted. This was > achieved by augmenting the barrier-ordered-before relation with: > > * RW1 is a memory write effect W1 and is generated by an atomic instruction > with both Acquire and Release semantics. > > You can see this in the latest Arm ARM. > > However, test_and_set_bit() is unordered on failure (i.e. when the bit is > unchanged) and uses READ_ONCE() as a quick check before the RmW. See the > "ORDERING" section of Documentation/atomic_bitops.txt. Damn, I forgot that too... :/ > I think you're missing the "shortcut" in test_and_set_bit(): > > if (READ_ONCE(*p) & mask) > return 1; > > old = arch_atomic_long_fetch_or(mask, (atomic_long_t *)p); > > so if the bit is already set (which I think is the 'ret == false' case) > then you've only got a control dependency here and we elide writing to > B. Given all that, I think workqueue wants to be fixed, it really does seem to rely on full ordering for it's test_and_set_bit() usage. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel