Re: [PATCH] mte: Follow arm64.nomte override in MMU setup.

From: Catalin Marinas <catalin.marinas@arm.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Evgenii Stepanov <eugenis@google.com>,
	Marc Zyngier <maz@kernel.org>, Will Deacon <will@kernel.org>,
	Vincenzo Frascino <vincenzo.frascino@arm.com>,
	Andrey Konovalov <andreyknvl@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] mte: Follow arm64.nomte override in MMU setup.
Date: Tue, 16 Aug 2022 08:51:47 +0100	[thread overview]
Message-ID: <YvtMk2cNDrrzVX3g@arm.com> (raw)
In-Reply-To: <CAMn1gO5Va0eVFqzoOLLLJ+C+x-5=cc4qXDTw0e9J7v0RpYWusA@mail.gmail.com>

On Tue, Aug 09, 2022 at 06:24:23PM -0700, Peter Collingbourne wrote:
> On Tue, Aug 9, 2022 at 10:29 AM Evgenii Stepanov <eugenis@google.com> wrote:
> > On Tue, Aug 9, 2022 at 9:49 AM Marc Zyngier <maz@kernel.org> wrote:
> > > In which case what is the tag memory doing in the linear map?
> > > Shouldn't it be marked as reserved, not mapped, and in general
> > > completely ignored by the NS OS?
> >
> > That would be wasteful. The idea is to only reserve the parts of the
> > tag memory that correspond to the TZ carveout and release the rest to
> > the NS OS.
> 
> More generally, one can imagine a system where *any* tagged memory
> transaction can result in an SError because the MTE implementation was
> not configured by an earlier bootloader phase, e.g. because the
> bootloader was configured to disable MTE at runtime. On such systems,
> the kernel must refrain from causing tagged memory transactions to be
> issued via the linear map, and that's exactly what this patch does.

The problem is that it doesn't. The 8.5 architecture allows any Normal
Cacheable (even non-tagged) mapping to fetch tags. It may happen that on
certain implementations setting MAIR to non-tagged works but that's not
guaranteed and with the Linux kernel we tend to stick to the architected
behaviour (with a few exceptions like PMU counters and errata).

There is an ongoing discussion with the architects and partners on
whether we can tighten the architecture as not to cause visible
side-effects like SError but not sure whether that has been closed yet
(just back from holiday).

Until that's sorted, tag storage cannot be reused in an arm64-generic
way in the kernel.

-- 
Catalin

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