Re: [PATCH v2] arm64: compat: Implement misalignment fixups for multiword loads

From: Catalin Marinas <catalin.marinas@arm.com>
To: Ard Biesheuvel <ardb@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
	will@kernel.org, mark.rutland@arm.com, maz@kernel.org,
	broonie@kernel.org, debian-arm@lists.debian.org,
	Vagrant Cascadian <vagrant@debian.org>,
	Riku Voipio <riku.voipio@iki.fi>,
	Steve McIntyre <steve@einval.com>
Subject: Re: [PATCH v2] arm64: compat: Implement misalignment fixups for multiword loads
Date: Wed, 31 Aug 2022 18:06:56 +0100	[thread overview]
Message-ID: <Yw+VMDk6vLMl/qwr@arm.com> (raw)
In-Reply-To: <20220701135322.3025321-1-ardb@kernel.org>

On Fri, Jul 01, 2022 at 03:53:22PM +0200, Ard Biesheuvel wrote:
> The 32-bit ARM kernel implements fixups on behalf of user space when
> using LDM/STM or LDRD/STRD instructions on addresses that are not 32-bit
> aligned. This is not something that is supported by the architecture,
> but was done anyway to increase compatibility with user space software,
> which mostly targeted x86 at the time and did not care about aligned
> accesses.
> 
> This feature is one of the remaining impediments to being able to switch
> to 64-bit kernels on 64-bit capable hardware running 32-bit user space,
> so let's implement it for the arm64 compat layer as well.
> 
> Note that the intent is to implement the exact same handling of
> misaligned multi-word loads and stores as the 32-bit kernel does,
> including what appears to be missing support for user space programs
> that rely on SETEND to switch to a different byte order and back. Also,
> like the 32-bit ARM version, we rely on the faulting address reported by
> the CPU to infer the memory address, instead of decoding the instruction
> fully to obtain this information.
> 
> This implementation is taken from the 32-bit ARM tree, with all pieces
> removed that deal with instructions other than LDRD/STRD and LDM/STM, or
> that deal with alignment exceptions taken in kernel mode.
> 
> Cc: debian-arm@lists.debian.org
> Cc: Vagrant Cascadian <vagrant@debian.org>
> Cc: Riku Voipio <riku.voipio@iki.fi>
> Cc: Steve McIntyre <steve@einval.com>
> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
> ---
> Note to cc'ees: if this is something you would like to see merged,
> please indicate so. This stuff is unlikely to get in if there are no
> users.
> 
> v2: - drop some obsolete comments
>     - emit a perf alignment-fault event for every handled instruction
>     - use arm64_skip_faulting_instruction() to get the correct behavior
>       wrt IT state and single step
>     - use types with correct endianness annotation (instructions are
>       always little endian on v7/v8+)

It looks like that's a fairly popular request from people running 32-bit
user on AArch64 kernels, so happy to queue it for 6.1 (if it still
applies cleanly). I'm not too keen on code duplication but it's a lot
more hassle to create a common decoding/emulation library to share with
arch/arm, especially as such code is not going to change in the future.

> +config COMPAT_ALIGNMENT_FIXUPS
> +	bool "Fix up misaligned multi-word loads and stores in user space"
> +	default y

For consistency with ARMV8_DEPRECATED, I think we should keep this as
default n.

Thanks.

-- 
Catalin

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