From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 13139ECAAD3 for ; Wed, 31 Aug 2022 17:08:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1GqPko2wX+1aPfaeksjX4hDiNoYr+6fcC/ALdrC2zeI=; b=GglaMZb7qgEc5+ u7O5OZqI17crhP9l3Op0ippIQ2AjQaYAMBur6muLQmJ5rsmM9VR/CJkmus7+8bo6nUFRZwLy5B7Vh VVEZgUA6R4Q0noh8/vQaTIgAp9TB8tOhwhkd21EdFnLGrbJRKnwBxyyQ9j78e0LYOKhqmHUEiQxf+ wu9ZcQMdnCVg9QFW1KTlguB4N9R8R8d6p5JCAhUDRitPii0oem7CutERHGZ86r5EAnZfAbBMT+dJy z1M6CaWTZyZts33SDptm0MmCLyhAbgWY75YyKF+Gy261dIS5KSyNf0Tk4b3xCbGRlTz2gR/VL/iBV L7bjlEtjogMVid53t+tg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRBH-007KSH-8Z; Wed, 31 Aug 2022 17:07:11 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oTRBD-007KRS-K6 for linux-arm-kernel@lists.infradead.org; Wed, 31 Aug 2022 17:07:09 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 785ACB8220A; Wed, 31 Aug 2022 17:07:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32951C433C1; Wed, 31 Aug 2022 17:07:00 +0000 (UTC) Date: Wed, 31 Aug 2022 18:06:56 +0100 From: Catalin Marinas To: Ard Biesheuvel Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, broonie@kernel.org, debian-arm@lists.debian.org, Vagrant Cascadian , Riku Voipio , Steve McIntyre Subject: Re: [PATCH v2] arm64: compat: Implement misalignment fixups for multiword loads Message-ID: References: <20220701135322.3025321-1-ardb@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220701135322.3025321-1-ardb@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220831_100707_850176_592134FA X-CRM114-Status: GOOD ( 29.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 01, 2022 at 03:53:22PM +0200, Ard Biesheuvel wrote: > The 32-bit ARM kernel implements fixups on behalf of user space when > using LDM/STM or LDRD/STRD instructions on addresses that are not 32-bit > aligned. This is not something that is supported by the architecture, > but was done anyway to increase compatibility with user space software, > which mostly targeted x86 at the time and did not care about aligned > accesses. > > This feature is one of the remaining impediments to being able to switch > to 64-bit kernels on 64-bit capable hardware running 32-bit user space, > so let's implement it for the arm64 compat layer as well. > > Note that the intent is to implement the exact same handling of > misaligned multi-word loads and stores as the 32-bit kernel does, > including what appears to be missing support for user space programs > that rely on SETEND to switch to a different byte order and back. Also, > like the 32-bit ARM version, we rely on the faulting address reported by > the CPU to infer the memory address, instead of decoding the instruction > fully to obtain this information. > > This implementation is taken from the 32-bit ARM tree, with all pieces > removed that deal with instructions other than LDRD/STRD and LDM/STM, or > that deal with alignment exceptions taken in kernel mode. > > Cc: debian-arm@lists.debian.org > Cc: Vagrant Cascadian > Cc: Riku Voipio > Cc: Steve McIntyre > Signed-off-by: Ard Biesheuvel > --- > Note to cc'ees: if this is something you would like to see merged, > please indicate so. This stuff is unlikely to get in if there are no > users. > > v2: - drop some obsolete comments > - emit a perf alignment-fault event for every handled instruction > - use arm64_skip_faulting_instruction() to get the correct behavior > wrt IT state and single step > - use types with correct endianness annotation (instructions are > always little endian on v7/v8+) It looks like that's a fairly popular request from people running 32-bit user on AArch64 kernels, so happy to queue it for 6.1 (if it still applies cleanly). I'm not too keen on code duplication but it's a lot more hassle to create a common decoding/emulation library to share with arch/arm, especially as such code is not going to change in the future. > +config COMPAT_ALIGNMENT_FIXUPS > + bool "Fix up misaligned multi-word loads and stores in user space" > + default y For consistency with ARMV8_DEPRECATED, I think we should keep this as default n. Thanks. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel