From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D1DC5ECAAD2 for ; Sat, 27 Aug 2022 12:37:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3rlQh7XZr/HvDrpzqo12oii0HxfEeCyJm6PfV8f6NKM=; b=KUdqL5PGY8sPl8 Fkx0gF7dEk/ifMc2+XWd8+NC7UjsdFaGAs8oB/5vaw+Hz20SIXuhIVwtj8mgq/Bquoe8lftMZY7ZI 3uFNlXW+xZ9NeXc8AabfpuTubhjGfWtEWSz5o3TuTcccnew1B2hiPcAtpCLWDCc4rSTZIgchSb951 nN1L8Ii/RG9msGs/mwlflL/vqmni05I70kFfk4OZAmJLFfOgsWdbtb6mp1wcOCH1bhDnJ1Bw8uFsS EaH6zMkRtVzpqjuTfj4/Vjtik2P5P5LEdtNy2Z0lZihLK4O3LFsvRAIgVQKSaQXC6C6znDs8tqd+O iL2lh1PwmvT5jd15nq4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oRv2j-00A3SL-71; Sat, 27 Aug 2022 12:36:05 +0000 Received: from mga17.intel.com ([192.55.52.151]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oRv2f-00A3Nl-EK for linux-arm-kernel@lists.infradead.org; Sat, 27 Aug 2022 12:36:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661603761; x=1693139761; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=z1GOHa4sbRW9EZHujjqjnAI2Ul+W2EA/lajLX5wB5rk=; b=kO+0QWM6SnAtuZZa5kAuJKQfDoQvVH28XipytHWPu7pioKPf2sZ85Ptp dI/v28kS3uy7kXoGjIdn0DP/jZhJYiCnmX+GkYMz2pIdO5XufHw3p+p1b WX/7KPDBMmPFZVaj28hPq4dmYihor7o0ldpH81ZoTaANnlkwn7tye93zE E9dhJGfxh4MVTPvo+Aen7Gkjs5tMPS9jbRJs9OnS5Bz4orHN2evyCfyat UmFSlfpmxYp8B64P90iLztjJ3Bn3SxpUf4JaXp3WMoo9+lqKAQQGXDoKF 95bR0AXLUb3QGs85SAC+U5UoiOXwvcxFgO8A1VUjemSKt9PzwKKy/j5sN Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10451"; a="275063352" X-IronPort-AV: E=Sophos;i="5.93,267,1654585200"; d="scan'208";a="275063352" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2022 05:35:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,267,1654585200"; d="scan'208";a="671805359" Received: from yilunxu-optiplex-7050.sh.intel.com (HELO localhost) ([10.239.159.165]) by fmsmga008.fm.intel.com with ESMTP; 27 Aug 2022 05:35:45 -0700 Date: Sat, 27 Aug 2022 20:26:29 +0800 From: Xu Yilun To: Nava kishore Manne Cc: git@amd.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, michal.simek@xilinx.com, mdf@kernel.org, hao.wu@intel.com, trix@redhat.com, p.zabel@pengutronix.de, gregkh@linuxfoundation.org, ronak.jain@xilinx.com, rajan.vaja@xilinx.com, abhyuday.godhasara@xilinx.com, piyush.mehta@xilinx.com, lakshmi.sai.krishna.potthuri@xilinx.com, harsha.harsha@xilinx.com, linus.walleij@linaro.org, nava.manne@xilinx.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-fpga@vger.kernel.org Subject: Re: [PATCH 4/4] fpga: zynqmp: Add afi config driver Message-ID: References: <20220824035542.706433-1-nava.kishore.manne@amd.com> <20220824035542.706433-5-nava.kishore.manne@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220824035542.706433-5-nava.kishore.manne@amd.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220827_053601_566036_FA3E5459 X-CRM114-Status: GOOD ( 35.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-08-24 at 09:25:42 +0530, Nava kishore Manne wrote: > Add zynqmp AXI FIFO interface(AFI) config driver. This is useful for the > configuration of the PS-PL interface on Zynq US+ MPSoC platform. Please help illustrate how to use the device for FPGA reprogramming, why it should be implemented as an FPGA bridge. >From the code I actually didn't see any operation that gates the fpga-region from other part of the machine. > > Signed-off-by: Nava kishore Manne > --- > MAINTAINERS | 6 ++ > drivers/fpga/Kconfig | 13 +++ > drivers/fpga/Makefile | 1 + > drivers/fpga/zynqmp-afi.c | 211 ++++++++++++++++++++++++++++++++++++++ > 4 files changed, 231 insertions(+) > create mode 100644 drivers/fpga/zynqmp-afi.c > > diff --git a/MAINTAINERS b/MAINTAINERS > index 20ffac651214..957e753e6406 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -8032,6 +8032,12 @@ F: Documentation/fpga/ > F: drivers/fpga/ > F: include/linux/fpga/ > > +FPGA ZYNQMP PS-PL BRIDGE DRIVER > +M: Nava kishore Manne > +S: Supported > +F: Documentation/devicetree/bindings/fpga/xlnx,zynqmp-afi-fpga.yaml > +F: drivers/fpga/zynqmp-afi.c > + > INTEL MAX10 BMC SECURE UPDATES > M: Russ Weight > L: linux-fpga@vger.kernel.org > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 6c416955da53..c08794d30fb5 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -130,6 +130,19 @@ config XILINX_PR_DECOUPLER > reconfiguration, preventing the system deadlock that can > occur if AXI transactions are interrupted by DFX. > > +config ZYNQMP_AFI > + tristate "Xilinx ZYNQMP AFI support" > + depends on FPGA_BRIDGE > + help > + Say Y to enable drivers to handle the PS-PL clocks configurations > + and PS-PL Bus-width. Xilinx Zynq US+ MPSoC connect the PS to the > + programmable logic (PL) through the AXI port. This AXI port helps > + to establish the data path between the PS and PL. > + In-order to establish the proper communication path between PS and PL, > + the AXI port data path should be configured with the proper Bus-width > + values and it will also handles the PS-PL reset signals to reset the > + PL domain. Same concern, please describe its relationship to FPGA reprogramming. > + > config FPGA_REGION > tristate "FPGA Region" > depends on FPGA_BRIDGE > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index 42ae8b58abce..94cfe60972db 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -31,6 +31,7 @@ obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o > obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o > obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o > obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o > +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o > > # High Level Interfaces > obj-$(CONFIG_FPGA_REGION) += fpga-region.o > diff --git a/drivers/fpga/zynqmp-afi.c b/drivers/fpga/zynqmp-afi.c > new file mode 100644 > index 000000000000..bc975d304039 > --- /dev/null > +++ b/drivers/fpga/zynqmp-afi.c > @@ -0,0 +1,211 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (C) 2022 Xilinx, Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* Registers and special values for doing register-based operations */ > +#define AFI_RDCHAN_CTRL_OFFSET 0x00 > +#define AFI_WRCHAN_CTRL_OFFSET 0x14 > +#define AFI_BUSWIDTH_MASK BIT(0) > + > +/** > + * struct zynqmp_afi - AFI register description. > + * @dev: device that owns this. > + * @of_node: Device Tree overlay. > + * @resets: Pointer to the reset control for ps-pl resets. > + */ > +struct zynqmp_afi { > + struct device *dev; > + struct device_node *of_node; > + struct reset_control *resets; > +}; > + > +/** > + * struct zynqmp_afi_configreg - AFI configuration registers info. > + * @reg: Name of the AFI configuration register. > + * @id: Register index value. > + */ > +struct zynqmp_afi_configreg { > + char *reg; > + u32 id; > +}; > + > +static struct zynqmp_afi_configreg afi_cfgreg[] = { > + {.reg = "xlnx,afi-fm0-rd-bus-width", .id = AFIFM0_RDCTRL}, > + {.reg = "xlnx,afi-fm1-rd-bus-width", .id = AFIFM1_RDCTRL}, > + {.reg = "xlnx,afi-fm2-rd-bus-width", .id = AFIFM2_RDCTRL}, > + {.reg = "xlnx,afi-fm3-rd-bus-width", .id = AFIFM3_RDCTRL}, > + {.reg = "xlnx,afi-fm4-rd-bus-width", .id = AFIFM4_RDCTRL}, > + {.reg = "xlnx,afi-fm5-rd-bus-width", .id = AFIFM5_RDCTRL}, > + {.reg = "xlnx,afi-fm6-rd-bus-width", .id = AFIFM6_RDCTRL}, > + {.reg = "xlnx,afi-fm0-wr-bus-width", .id = AFIFM0_WRCTRL}, > + {.reg = "xlnx,afi-fm1-wr-bus-width", .id = AFIFM1_WRCTRL}, > + {.reg = "xlnx,afi-fm2-wr-bus-width", .id = AFIFM2_WRCTRL}, > + {.reg = "xlnx,afi-fm3-wr-bus-width", .id = AFIFM3_WRCTRL}, > + {.reg = "xlnx,afi-fm4-wr-bus-width", .id = AFIFM4_WRCTRL}, > + {.reg = "xlnx,afi-fm5-wr-bus-width", .id = AFIFM5_WRCTRL}, > + {.reg = "xlnx,afi-fm6-wr-bus-width", .id = AFIFM6_WRCTRL}, > + {.reg = "xlnx,afi-fs-ss0-bus-width", .id = AFIFS}, > + {.reg = "xlnx,afi-fs-ss2-bus-width", .id = AFIFS_SS2}, > + {} > +}; > + > +static int zynqmp_afi_config(struct zynqmp_afi *afi_data) > +{ > + struct zynqmp_afi_configreg *cfgptr = afi_cfgreg; > + struct device_node *np = afi_data->of_node; > + u32 afi_ss0_val, afi_ss1_val, bus_width; > + int ret; > + > + while (cfgptr->reg) { > + ret = of_property_read_u32(np, cfgptr->reg, &bus_width); > + if (!ret) { > + if (cfgptr->id == AFIFS_SS2) { > + if (bus_width == 32) > + ret = zynqmp_pm_afi(AFIFS_SS2, > + AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL); > + else if (bus_width == 64) > + ret = zynqmp_pm_afi(AFIFS_SS2, > + AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL); > + else if (bus_width == 128) > + ret = zynqmp_pm_afi(AFIFS_SS2, > + AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL); > + else > + return -EINVAL; > + } else if (cfgptr->id == AFIFS) { > + if (bus_width == 32) > + afi_ss0_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL; > + else if (bus_width == 64) > + afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_64_CONFIG_VAL; > + else if (bus_width == 128) > + afi_ss0_val = AFIFS_SS0_SS2_BUS_WIDTH_128_CONFIG_VAL; > + else > + return -EINVAL; > + > + ret = of_property_read_u32(np, "xlnx,afi-fs-ss1-bus-width", > + &bus_width); > + if (!ret) { > + if (bus_width == 32) > + afi_ss1_val = AFIFS_SS_BUS_WIDTH_32_CONFIG_VAL; > + else if (bus_width == 64) > + afi_ss1_val = AFIFS_SS1_BUS_WIDTH_64_CONFIG_VAL; > + else if (bus_width == 128) > + afi_ss1_val = AFIFS_SS1_BUS_WIDTH_128_CONFIG_VAL; > + else > + return -EINVAL; > + > + ret = zynqmp_pm_afi(AFIFS, afi_ss1_val | afi_ss0_val); > + } > + } else { > + if (bus_width == 32) > + ret = zynqmp_pm_afi(cfgptr->id, > + AFIFM_BUS_WIDTH_32_CONFIG_VAL); > + else if (bus_width == 64) > + ret = zynqmp_pm_afi(cfgptr->id, > + AFIFM_BUS_WIDTH_64_CONFIG_VAL); > + else if (bus_width == 128) > + ret = zynqmp_pm_afi(cfgptr->id, > + AFIFM_BUS_WIDTH_128_CONFIG_VAL); > + else > + return -EINVAL; > + } > + } > + cfgptr++; > + } > + > + return 0; > +} > + > +static int zynqmp_afi_enable_set(struct fpga_bridge *bridge, bool enable) > +{ > + struct device_node *overlay = bridge->info->overlay; > + struct zynqmp_afi *priv = bridge->priv; > + int ret = 0; > + > + if (enable) { > + reset_control_reset(priv->resets); > + return 0; > + } > + > + of_node_get(overlay); > + priv->of_node = > + of_find_node_with_property(overlay, > + "xlnx,afi-fm0-rd-bus-width"); I'm a little confused here. The fpga_image_info.overlay is for fpga-region, but from your binding doc this property is for this afi device. You want to add another overlay targeting afi dev node during reprograming? > + if (priv->of_node) > + ret = zynqmp_afi_config(priv); > + of_node_put(priv->of_node); > + > + return ret; > +} > + > +static const struct fpga_bridge_ops zynqmp_afi_br_ops = { > + .enable_set = zynqmp_afi_enable_set, > +}; > + > +static const struct of_device_id zynqmp_afi_of_match[] = { > + { .compatible = "xlnx,zynqmp-afi-fpga" }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, zynqmp_afi_of_match); > + > +static int zynqmp_afi_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct zynqmp_afi *priv; > + struct fpga_bridge *br; > + > + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + priv->dev = dev; > + > + priv->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev); > + if (IS_ERR(priv->resets)) > + return PTR_ERR(priv->resets); > + > + br = fpga_bridge_register(dev, "Xilinx ZynqMP AFI", > + &zynqmp_afi_br_ops, priv); > + if (IS_ERR(br)) { > + dev_err(dev, "unable to register Xilinx ZynqMP AFI"); Need a "\n" at the end? Thanks, Yilun > + return PTR_ERR(br); > + } > + > + platform_set_drvdata(pdev, br); > + > + return 0; > +} > + > +static int zynqmp_afi_remove(struct platform_device *pdev) > +{ > + struct fpga_bridge *bridge = platform_get_drvdata(pdev); > + > + fpga_bridge_unregister(bridge); > + > + return 0; > +} > + > +static struct platform_driver zynqmp_afi_driver = { > + .probe = zynqmp_afi_probe, > + .remove = zynqmp_afi_remove, > + .driver = { > + .name = "zynqmp_afi", > + .of_match_table = of_match_ptr(zynqmp_afi_of_match), > + }, > +}; > + > +module_platform_driver(zynqmp_afi_driver); > + > +MODULE_DESCRIPTION("ZYNQMP FPGA AXI FIFO interface configuration module"); > +MODULE_AUTHOR("Nava kishore Manne "); > +MODULE_LICENSE("GPL"); > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel