From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E84BECAAD3 for ; Sun, 4 Sep 2022 17:19:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TX96+vxPvuENg26tpH9BwXHAlV8bNQ04HRfqPLbzSuU=; b=0SoiYlYOipuKf6 AkHvz9MV5lt9wjrbnJDdO2qByOWxvJ5FejVI4NejMv/dbt7GYE5Hd7nlZr/1e64U619suvDlOdLoG ozLB4xo6RxFW7CRBn98p3oXPtM3Gqm9pzVZiYIo3NQ+kuXjY2bmDDnENhZ8Sd7wrUJ1i0h0ktFeQK 2gSA1gTlh6+tAt5dD25QzaGHqv+BDT17fGouanm2hNeMV1zWGRgImbE0yo+xK4uNyTrqz8LlW0iOT nWpSngoJytlOHj47y1thvEoWHkKjbemBLTfEMarwLYPGSlE3kc1QqgZUHyR1QEKJ2J0+3wbWqvXZj UoZFpZnGgErsl3qcBk1g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oUtGW-008RVe-L0; Sun, 04 Sep 2022 17:18:36 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oUtGT-008RR9-KK for linux-arm-kernel@lists.infradead.org; Sun, 04 Sep 2022 17:18:34 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 18AE5CE0B97; Sun, 4 Sep 2022 17:18:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B243C433D6; Sun, 4 Sep 2022 17:18:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662311900; bh=mrk5pkJcHTTsmwCZFN9V23o4HfG3eXfOH8HbEbJtxJk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Nptjcenw/XHolTmJsfu437e63yq4FMUbBY1rW3hXzrzuqDuUBiqktWBlw4h9sg9kh 0ASWXE5IYedKw/F1BTPgeKgHnsjWPKUl7hav+YWDGfAKlQJn+TSu5a5Tcu9l8E68x9 T5JcNbMzHly1AG1sLTu0i2KjcUgxzstMwVQqgWoVspq31qEfo4d4M1jLHFj+a5BitX DNF0lV/ZMYL6Fu4sJ5MJLCgvPO57T3JgE2DlEuI/b04Av9PJRcFxip2JK7JKRtjpbk DYNSW8GGGnrcLjFVoa11pATgpI3MyEVMV9JNpE8yN/UVWgr5S7CJoTAlb9ZUXqhd4u J3pfF82X0paMg== Date: Sun, 4 Sep 2022 22:48:14 +0530 From: Vinod Koul To: Amelie Delaunay Cc: Jonathan Corbet , Maxime Coquelin , Alexandre Torgue , linux-doc@vger.kernel.org, dmaengine@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Marek Vasut Subject: Re: [RESEND PATCH v3 0/6] STM32 DMA-MDMA chaining feature Message-ID: References: <20220829154646.29867-1-amelie.delaunay@foss.st.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220829154646.29867-1-amelie.delaunay@foss.st.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220904_101833_853181_EEFE558A X-CRM114-Status: GOOD ( 13.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 29-08-22, 17:46, Amelie Delaunay wrote: > This patchset (re)introduces STM32 DMA-MDMA chaining feature. > > As the DMA is not able to generate convenient burst transfer on the DDR, > it penalises the AXI bus when accessing the DDR. While it accesses > optimally the SRAM. The DMA-MDMA chaining then consists in having an SRAM > buffer between DMA and MDMA, so the DMA deals with peripheral and SRAM, > and the MDMA with SRAM and DDR. > > The feature relies on the fact that DMA channel Transfer Complete signal > can trigger a MDMA channel transfer and MDMA can clear the DMA request by > writing to DMA Interrupt Clear register. > > A deeper introduction can be found in patch 1. > > Previous implementation [1] has been dropped as nacked. > Unlike this previous implementation (where all the stuff was embedded in > stm32-dma driver), the user (in peripheral drivers using dma) has now to > configure the MDMA channel. Applied, thanks -- ~Vinod _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel