From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A731C07E9D for ; Sat, 24 Sep 2022 23:23:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pCtJZRgTpku35poM8CvMXuwmR6DMnTemxHXR0UMQauc=; b=GuM9HTwNagVGgJ GORrW9qVR5DtpNY4WqWr15nom0BeZQr2TuMCzD7tS8H7GErzTbwVuPGMEwILZ2Y1M8vMegM8JN2yW hhEuuvL+ES9Wq8Bs3R6mMIEw/PLhW7mryDEFCK6qXEkjAm3jEfse2KLrsln4gyDq3a1LroL1vSovN Jl1JyYdCef5XJG+knpKdcWwSD+q4jpswFj7wFe5FpDbYSJN8gMTtqcR0WYewpl5dwzr4MNXUq7Z9d 7DUJyuGZxbsyGKWrshv5HDQWE5HvDEX+15pGThrm0TeIIWQe+I5Rb2i6RG+WvBzP24iUi13l7rrCi dFUZct5YtjSOn+VD5DRw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocET3-009fxq-Hq; Sat, 24 Sep 2022 23:21:53 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ocET0-009fw1-4I for linux-arm-kernel@lists.infradead.org; Sat, 24 Sep 2022 23:21:51 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 28ONLkC7124329; Sat, 24 Sep 2022 18:21:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1664061706; bh=v3lCVtkq6BEwNFbBeBeKgPZwfN6yjcH4TCyVEWbvL5c=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=ANKbLcae3FJoOOvFhRU5QXZnWl0MOcdzgFc+5xi67NO7vUhpIiatvXfNaWKbKSHSz 8Oc1md3tei951ueKlD43lI2fe1LAtAkRJNtNBKzA+y1vJSUpOGlCbeEjstrZ6i6FZu fsIBbvzI/4sd+Pj7FpY+KOG90bd9dJP5L1ovit5Q= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 28ONLkA1114073 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 24 Sep 2022 18:21:46 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Sat, 24 Sep 2022 18:21:46 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Sat, 24 Sep 2022 18:21:46 -0500 Received: from ubuntu (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with SMTP id 28ONLfx1111346; Sat, 24 Sep 2022 18:21:43 -0500 Date: Sat, 24 Sep 2022 16:21:41 -0700 From: Matt Ranostay To: Kishon Vijay Abraham I CC: , , , Subject: Re: [PATCH 1/3] PCI: j721e: Add PCIe 4x lane selection support Message-ID: References: <20220909201607.3835-1-mranostay@ti.com> <20220909201607.3835-2-mranostay@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220924_162150_268179_3BCC54AA X-CRM114-Status: GOOD ( 17.81 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Sep 23, 2022 at 02:50:19PM +0530, Kishon Vijay Abraham I wrote: > Hi Matt, > > On 10/09/22 1:46 am, Matt Ranostay wrote: > > Increase LANE_COUNT_MASK to two-bit field that allows selection of > > 4x lane PCIe which was previously limited to 2x lane support. > > > > Cc: Kishon Vijay Abraham I > > Signed-off-by: Matt Ranostay > > Signed-off-by: Vignesh Raghavendra > > --- > > drivers/pci/controller/cadence/pci-j721e.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > > index a82f845cc4b5..62c2c70256b8 100644 > > --- a/drivers/pci/controller/cadence/pci-j721e.c > > +++ b/drivers/pci/controller/cadence/pci-j721e.c > > @@ -43,7 +43,7 @@ enum link_status { > > }; > > #define J721E_MODE_RC BIT(7) > > -#define LANE_COUNT_MASK BIT(8) > > +#define LANE_COUNT_MASK GENMASK(9, 8) > > The MASK value as well has to be specific to platforms. For J721E, it is 1 > bit only. > Noted. Will revise in next version of the patchset. - Matt > Thanks, > Kishon > > > #define LANE_COUNT(n) ((n) << 8) > > #define GENERATION_SEL_MASK GENMASK(1, 0) > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel