From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72C6DC433FE for ; Wed, 5 Oct 2022 18:17:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=OtUdR1ktCbtt19nI088/J9cji6PTqY/ttE5k72mqZZ4=; b=npt2D8qkuH9Zx9 8e52EQYYmsUhgJ0eMZbNX4fXB+OwK3oK2TZXvL3aggEzBvGj6AtENvI8/lSspjPdGybdWHLohTBOS +i5hTbWA6ndIyy0gxXcAJIx3FJELkiI1vAf4i/sSiVDnWPgETFScXNutZ/hcxCkOpvozofL003825 kK0DsTUv423/WXG9flpAXPNeHjuEtDcDcDQphD6S4F4ui6VlP84y1eoitWo5yJOhA/PnlrZIwe1Tn Ihgh79s3SrZSGDtUZ4bLs1E5+vIOiFTUgAy22A2jOiS6p0QifKmAsK6WpF54+XeSQeTgstwz/oMbK kD7pPCrg5ZUmnCQC+Drg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1og8wg-00Fczp-QX; Wed, 05 Oct 2022 18:16:38 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1og8wd-00FcyZ-3o for linux-arm-kernel@lists.infradead.org; Wed, 05 Oct 2022 18:16:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 700CE106F; Wed, 5 Oct 2022 11:16:33 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.3.221]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BA7B3F67D; Wed, 5 Oct 2022 11:16:25 -0700 (PDT) Date: Wed, 5 Oct 2022 19:16:19 +0100 From: Mark Rutland To: Rich Wiley Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, marc.zyngier@arm.com Subject: Re: [PATCH v2] kernel: arm64: add Spectre-V2 mitigation cb for NV CPUs Message-ID: References: <20221005175319.20565-1-rwiley@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20221005175319.20565-1-rwiley@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221005_111635_267485_ED36996C X-CRM114-Status: GOOD ( 26.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [adding James Morse, Marc Zyngier] On Wed, Oct 05, 2022 at 10:53:19AM -0700, Rich Wiley wrote: > NVIDIA cores can flush indirect branch predictors with a sysreg write > that can be done from the kernel without the need for a FW call. > > Given that NVIDIA cores are not susceptible to CVE-2022-23960 and FW > mitigation is not required for CVE-2017-5715, ATF can report via > SMCCC_ARCH_WORKAROUND_3 that FW mitigation is not required for either. > > Fixes: commit ba2689234be9 ("arm64: entry: Add vectors that have the bhb > mitigation sequences") The proper format for this is: | Fixes: ba2689234be9 ("arm64: entry: Add vectors that have the bhb mitigation sequences") ... though given you say NVIDIA cores are not susceptible to CVE-2022-23960 (aka spectre-BHB), I don't think that tag is correct, and I don't think you need a fixes tag at all, unless you're seeing an actual problem. If you are, can you please describe that in the commit message? The patch says 'v2'. Do you have a link to v1, and a description of any changes since then? > > Signed-off-by: Rich Wiley > --- > arch/arm64/kernel/proton-pack.c | 20 ++++++++++++++++---- > 1 file changed, 16 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c > index 40be3a7c2c53..0de77b0ff8d4 100644 > --- a/arch/arm64/kernel/proton-pack.c > +++ b/arch/arm64/kernel/proton-pack.c > @@ -258,14 +258,26 @@ static noinstr void qcom_link_stack_sanitisation(void) > : "=&r" (tmp)); > } > > +/* Called during entry so must be noinstr */ > +static noinstr void nvidia_indirect_branch_pred_flush(void) > +{ > + asm volatile("msr s3_0_c15_c0_6, %0" :: "r" (0x1UL)); Please use write_sysreg() or write_sysreg_s() for this. > + isb(); > +} This is an IMPLEMENTATION DEFINED register, so the usual problems apply here: * This is IMPLEMENTATION DEFINED, and usually IMP-DEF features are subject to EL3 access controls. Are there any EL3 access controls, and is it possible that this will trap to EL3 on some firmware? * This is IMPLEMENTATION DEFINED, and hypervisors normally trap-end-emulate IMP-DEF features as UNDEFINED. So this is not going to be safe in a VM, and we cannot use this when running booted at EL1. Have you tested this with a VM? Will KVM expose a usabel interface to the guest (e.g. the SMCCC mitigation, backing that with the MSR at EL2)? I don't see any KVM plumbing for that, so I suspect not. Thanks, Mark. > + > static bp_hardening_cb_t spectre_v2_get_sw_mitigation_cb(void) > { > u32 midr = read_cpuid_id(); > - if (((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR) && > - ((midr & MIDR_CPU_MODEL_MASK) != MIDR_QCOM_FALKOR_V1)) > - return NULL; > + if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) || > + ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) > + return qcom_link_stack_sanitisation; > + > + if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_NVIDIA_DENVER) || > + ((midr & MIDR_CPU_MODEL_MASK) == MIDR_NVIDIA_CARMEL)) > + return nvidia_indirect_branch_pred_flush; > + > + return NULL; > > - return qcom_link_stack_sanitisation; > } > > static enum mitigation_state spectre_v2_enable_fw_mitigation(void) > -- > 2.17.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel