From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>
Cc: Sascha Bischoff <sascha.bischoff@arm.com>,
Timothy Hayes <timothy.hayes@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Liam.Howlett@oracle.com, ast@kernel.org
Subject: Re: [PATCH 20/24] irqchip/gic-v5: Add GICv5 LPI/IPI support
Date: Fri, 11 Apr 2025 11:26:07 +0200 [thread overview]
Message-ID: <Z/jgL52ZVdcxTEkP@lpieralisi> (raw)
In-Reply-To: <20250408-gicv5-host-v1-20-1f26db465f8d@kernel.org>
[+Liam, Alexei, since I mentioned to them this maple tree "usage"
in the past, in case they see a point in chiming in]
On Tue, Apr 08, 2025 at 12:50:19PM +0200, Lorenzo Pieralisi wrote:
[...]
> The LPI INTID namespace is managed using a maple tree which encodes
> ranges, add code to alloc/free LPI INTIDs.
>
> Maple tree entries are not used by the driver, only the range tracking
> is required - therefore the driver first finds an empty area large
> enough to contain the required number of LPIs then checks the
> adjacent (and possibly occupied) LPI ranges and try to merge them
> together, reducing maple tree slots usage.
The maple tree usage for this purpose is an RFC at this stage.
Added Alexei because I know BPF arena used the maple tree in
a similar way in the past and moved to a range tree because
the BPF arena requires a special purpose mem allocator.
As Thomas already pointed out a plain bitmap could do even though
it requires preallocating memory up to 2MB (or we can grow it
dynamically).
We could allocate IDs using an IDA as well, though that's 1 by 1,
we allocate LPI INTIDs 1 by 1 - mostly, upon MSI allocation, so
using an IDA could do (AFAIU it works for 0..INT_MAX we need
0..2^24 worst case).
I don't want to abuse the maple tree for this purpose, opinions
welcome, it is just to understand if there are core code structures
that can be reused.
IDs allocation snippet below.
[...]
> +static struct maple_tree lpi_mt;
> +static u32 num_lpis;
> +
> +void __init gicv5_init_lpi(u32 lpis)
> +{
> + mt_init_flags(&lpi_mt, MT_FLAGS_ALLOC_RANGE);
> + num_lpis = lpis;
> +}
> +
> +void __init gicv5_free_lpi(void)
> +{
> + mtree_destroy(&lpi_mt);
> + num_lpis = 0;
> +}
> +
> +#define MT_ENTRY ((void *)&lpi_mt) /* Unused - just a valid pointer */
> +
> +static int alloc_lpi_range(u32 lpis, u32 *base)
> +{
> + int ret;
> + void *entry;
> + unsigned long lpi_base, startp, lastp;
> +
> + MA_STATE(mas, &lpi_mt, 0, 0);
> +
> + if (!num_lpis)
> + return -ENODEV;
s/ENODEV/ENOSPC
> +
> + mtree_lock(&lpi_mt);
> + ret = mas_empty_area(&mas, 0, num_lpis - 1, lpis);
> + if (ret) {
//Fixed
+ mtree_unlock(&lpi_mt);
> + pr_err("Failed to perform a dynamic alloc in the LPI MT!\n");
> + return ret;
> + }
> +
> + lpi_base = mas.index;
> +
> + /*
> + * We don't really care about the entry itself, only about
> + * allocation of a maple tree ranges describing in use LPIs.
> + * That's why, upon allocation, we try to merge slots adjacent
> + * with the empty one we are allocating to minimize the number
> + * of slots we take from maple tree nodes for nothing, all
> + * we need to keep track of is in use ranges.
> + */
> + startp = mas.index;
> + lastp = mas.last;
> +
> + entry = mas_next(&mas, num_lpis - 1);
> + if (entry && mas.index == lastp + 1)
> + lastp = mas.last;
> +
> + entry = mas_prev(&mas, 0);
> + if (entry)
> + startp = mas.index;
> + mas_set_range(&mas, startp, lastp);
> + mas_store_gfp(&mas, MT_ENTRY, GFP_KERNEL);
> + mtree_unlock(&lpi_mt);
> +
> + // startp is the index at which we allocated, i.e. the base LPI.
> + *base = lpi_base;
> +
> + return 0;
> +}
> +
> +// Drop entries between min and max (inclusive)
> +static int release_lpi_range(u32 min, u32 max)
> +{
> + return mtree_store_range(&lpi_mt, min, max, NULL, GFP_KERNEL);
> +}
Thanks,
Lorenzo
next prev parent reply other threads:[~2025-04-11 10:00 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-08 10:49 [PATCH 00/24] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 01/24] Documentation: devicetree: bindings: Add GICv5 DT bindings Lorenzo Pieralisi
2025-04-08 12:26 ` Rob Herring (Arm)
2025-04-08 14:58 ` Lorenzo Pieralisi
2025-04-08 15:07 ` Rob Herring
2025-04-09 8:20 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 02/24] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 03/24] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 04/24] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 05/24] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 06/24] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 07/24] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 08/24] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 09/24] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 10/24] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 11/24] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 12/24] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 13/24] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-04-09 7:48 ` Arnd Bergmann
2025-04-09 8:51 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 14/24] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 15/24] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 16/24] arm64: cpucaps: Add GCIE capability Lorenzo Pieralisi
2025-04-08 11:26 ` Mark Rutland
2025-04-08 15:02 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 17/24] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 18/24] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-04-08 21:42 ` Thomas Gleixner
2025-04-09 7:30 ` Lorenzo Pieralisi
2025-04-17 14:49 ` Lorenzo Pieralisi
2025-04-11 17:06 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 19/24] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-04-09 7:02 ` Thomas Gleixner
2025-04-09 7:40 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 20/24] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-04-09 8:23 ` Arnd Bergmann
2025-04-09 10:11 ` Lorenzo Pieralisi
2025-04-09 10:56 ` Arnd Bergmann
2025-04-09 13:15 ` Lorenzo Pieralisi
2025-04-09 14:25 ` Arnd Bergmann
2025-04-18 9:21 ` Lorenzo Pieralisi
2025-04-09 8:27 ` Thomas Gleixner
2025-04-09 10:30 ` Lorenzo Pieralisi
2025-04-11 9:26 ` Lorenzo Pieralisi [this message]
2025-04-11 9:55 ` Thomas Gleixner
2025-04-11 12:37 ` Lorenzo Pieralisi
2025-04-12 13:01 ` Liam R. Howlett
2025-04-14 8:26 ` Lorenzo Pieralisi
2025-04-14 14:37 ` Liam R. Howlett
2025-04-15 8:08 ` Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 21/24] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 22/24] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-04-09 11:13 ` Thomas Gleixner
2025-04-09 13:37 ` Lorenzo Pieralisi
2025-04-09 18:57 ` Thomas Gleixner
2025-04-10 8:08 ` Lorenzo Pieralisi
2025-04-10 9:20 ` Thomas Gleixner
2025-04-08 10:50 ` [PATCH 23/24] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-04-08 10:50 ` [PATCH 24/24] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
2025-04-09 13:44 ` kernel test robot
2025-04-09 14:04 ` Lorenzo Pieralisi
2025-04-09 14:07 ` Krzysztof Kozlowski
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