From: Frank Li <Frank.li@nxp.com>
To: Richard Zhu <hongxing.zhu@nxp.com>
Cc: l.stach@pengutronix.de, lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
imx@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/6] PCI: imx6: Start link directly when workaround is not required
Date: Fri, 28 Mar 2025 10:47:03 -0400 [thread overview]
Message-ID: <Z+a2Z0X9hZ5CDvsA@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20250328030213.1650990-2-hongxing.zhu@nxp.com>
On Fri, Mar 28, 2025 at 11:02:08AM +0800, Richard Zhu wrote:
> The current link setup procedure is one workaround to detect the device
> behind PCIe switches on some i.MX6 platforms.
>
> To describe more accurately, change the flag name from
> IMX_PCIE_FLAG_IMX_SPEED_CHANGE to IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND.
>
> Start PCIe link directly when this flag is not set on i.MX7 or later
> platforms to simple and speed up link training.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/pci/controller/dwc/pci-imx6.c | 34 +++++++++++----------------
> 1 file changed, 14 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index c1f7904e3600..57aa777231ae 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -91,7 +91,7 @@ enum imx_pcie_variants {
> };
>
> #define IMX_PCIE_FLAG_IMX_PHY BIT(0)
> -#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1)
> +#define IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND BIT(1)
> #define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
> #define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3)
> #define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4)
> @@ -860,6 +860,12 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
> u32 tmp;
> int ret;
>
> + if (!(imx_pcie->drvdata->flags &
> + IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND)) {
> + imx_pcie_ltssm_enable(dev);
> + return 0;
> + }
> +
> /*
> * Force Gen1 operation when starting the link. In case the link is
> * started in Gen2 mode, there is a possibility the devices on the
> @@ -896,22 +902,10 @@ static int imx_pcie_start_link(struct dw_pcie *pci)
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
> dw_pcie_dbi_ro_wr_dis(pci);
>
> - if (imx_pcie->drvdata->flags &
> - IMX_PCIE_FLAG_IMX_SPEED_CHANGE) {
> -
> - /*
> - * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
> - * from i.MX6 family when no link speed transition
> - * occurs and we go Gen1 -> yep, Gen1. The difference
> - * is that, in such case, it will not be cleared by HW
> - * which will cause the following code to report false
> - * failure.
> - */
> - ret = imx_pcie_wait_for_speed_change(imx_pcie);
> - if (ret) {
> - dev_err(dev, "Failed to bring link up!\n");
> - goto err_reset_phy;
> - }
> + ret = imx_pcie_wait_for_speed_change(imx_pcie);
> + if (ret) {
> + dev_err(dev, "Failed to bring link up!\n");
> + goto err_reset_phy;
> }
>
> /* Make sure link training is finished as well! */
> @@ -1665,7 +1659,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX6Q] = {
> .variant = IMX6Q,
> .flags = IMX_PCIE_FLAG_IMX_PHY |
> - IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
> + IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
> IMX_PCIE_FLAG_BROKEN_SUSPEND |
> IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .dbi_length = 0x200,
> @@ -1681,7 +1675,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX6SX] = {
> .variant = IMX6SX,
> .flags = IMX_PCIE_FLAG_IMX_PHY |
> - IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
> + IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
> IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> .ltssm_off = IOMUXC_GPR12,
> @@ -1696,7 +1690,7 @@ static const struct imx_pcie_drvdata drvdata[] = {
> [IMX6QP] = {
> .variant = IMX6QP,
> .flags = IMX_PCIE_FLAG_IMX_PHY |
> - IMX_PCIE_FLAG_IMX_SPEED_CHANGE |
> + IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
> IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> --
> 2.37.1
>
next prev parent reply other threads:[~2025-03-28 15:28 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-28 3:02 [PATCH v3 0/6] Add some enhancements for i.MX95 PCIe Richard Zhu
2025-03-28 3:02 ` [PATCH v3 1/6] PCI: imx6: Start link directly when workaround is not required Richard Zhu
2025-03-28 14:47 ` Frank Li [this message]
2025-04-02 6:27 ` Manivannan Sadhasivam
2025-04-02 7:39 ` Hongxing Zhu
2025-03-28 3:02 ` [PATCH v3 2/6] PCI: imx6: Toggle the cold reset for i.MX95 PCIe Richard Zhu
2025-03-28 14:53 ` Frank Li
2025-04-02 6:36 ` Manivannan Sadhasivam
2025-04-02 7:40 ` Hongxing Zhu
2025-03-28 3:02 ` [PATCH v3 3/6] PCI: imx6: Workaround i.MX95 PCIe may not exit L23 ready Richard Zhu
2025-04-02 7:07 ` Manivannan Sadhasivam
2025-04-02 7:59 ` Hongxing Zhu
2025-04-02 15:17 ` Manivannan Sadhasivam
2025-04-03 3:22 ` Hongxing Zhu
2025-04-08 3:02 ` Hongxing Zhu
2025-04-09 16:43 ` Manivannan Sadhasivam
2025-04-10 2:45 ` Hongxing Zhu
2025-04-13 15:38 ` Manivannan Sadhasivam
2025-04-14 3:15 ` Hongxing Zhu
2025-04-15 7:17 ` Manivannan Sadhasivam
2025-03-28 3:02 ` [PATCH v3 4/6] PCI: imx6: Let i.MX95 PCIe compliance with 8GT/s Receiver Impedance ECN Richard Zhu
2025-03-28 14:55 ` Frank Li
2025-04-02 7:08 ` Manivannan Sadhasivam
2025-03-28 3:02 ` [PATCH v3 5/6] PCI: imx6: Add PLL clock lock check for i.MX95 PCIe Richard Zhu
2025-04-02 7:10 ` Manivannan Sadhasivam
2025-04-02 7:40 ` Hongxing Zhu
2025-03-28 3:02 ` [PATCH v3 6/6] PCI: imx6: Save and restore the LUT setting " Richard Zhu
2025-03-28 14:56 ` Frank Li
2025-04-02 7:12 ` Manivannan Sadhasivam
2025-04-02 7:40 ` Hongxing Zhu
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