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From: Oliver Upton To: Marc Zyngier Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Bjorn Andersson , Christoffer Dall Subject: Re: [PATCH 02/11] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Message-ID: References: <20241202172134.384923-1-maz@kernel.org> <20241202172134.384923-3-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241202172134.384923-3-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241204_162626_502883_F34D3AA1 X-CRM114-Status: GOOD ( 23.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Dec 02, 2024 at 05:21:25PM +0000, Marc Zyngier wrote: > Emulating the timers with FEAT_NV2 is a bit odd, as the timers > can be reconfigured behind our back without the hypervisor even > noticing. In the VHE case, that's an actual regression in the > architecture... > > Co-developed-by: Christoffer Dall > Signed-off-by: Christoffer Dall > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/arch_timer.c | 44 ++++++++++++++++++++++++++++++++++++ > arch/arm64/kvm/arm.c | 3 +++ > include/kvm/arm_arch_timer.h | 1 + > 3 files changed, 48 insertions(+) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 1215df5904185..81afafd62059f 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -905,6 +905,50 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) > kvm_timer_blocking(vcpu); > } > > +void kvm_timer_sync_nested(struct kvm_vcpu *vcpu) > +{ > + /* > + * When NV2 is on, guest hypervisors have their EL0 timer register > + * accesses redirected to the VNCR page. Any guest action taken on > + * the timer is postponed until the next exit, leading to a very > + * poor quality of emulation. > + */ > + if (!is_hyp_ctxt(vcpu)) > + return; > + > + if (!vcpu_el2_e2h_is_set(vcpu)) { > + /* > + * A non-VHE guest hypervisor doesn't have any direct access > + * to its timers: the EL2 registers trap (and the HW is > + * fully emulated), while the EL0 registers access memory > + * despite the access being notionally direct. Boo. > + * > + * We update the hardware timer registers with the > + * latest value written by the guest to the VNCR page > + * and let the hardware take care of the rest. > + */ > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTV_CTL_EL0), SYS_CNTV_CTL); > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTV_CVAL_EL0), SYS_CNTV_CVAL); > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTP_CTL_EL0), SYS_CNTP_CTL); > + write_sysreg_el0(__vcpu_sys_reg(vcpu, CNTP_CVAL_EL0), SYS_CNTP_CVAL); > + } else { > + /* > + * For a VHE guest hypervisor, the EL2 state is directly > + * stored in the host EL0 timers, while the emulated EL0 > + * state is stored in the VNCR page. The latter could have > + * been updated behind our back, and we must reset the > + * emulation of the timers. > + */ nitpick: s/host EL0/EL1/ At least in the way the architecture terms it there's no such thing as an EL0 timer, and "host EL0" might lead one to think of ELIsInHost(EL0) -- Thanks, Oliver