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From: Oliver Upton To: Marc Zyngier Cc: Shameer Kolothum , kvmarm@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, cohuck@redhat.com, eric.auger@redhat.com, sebott@redhat.com, yuzenghui@huawei.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, anthony.jebson@huawei.com, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Subject: Re: [PATCH v4 3/3] arm64: paravirt: Enable errata based on implementation CPUs Message-ID: References: <20241218105345.73472-1-shameerali.kolothum.thodi@huawei.com> <20241218105345.73472-4-shameerali.kolothum.thodi@huawei.com> <86bjx8q995.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86bjx8q995.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241219_094105_624720_B298892A X-CRM114-Status: GOOD ( 15.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 19, 2024 at 10:04:22AM +0000, Marc Zyngier wrote: > > +void __init pv_target_impl_cpu_init(void) > > +{ > > + struct arm_smccc_res res; > > + int index = 0, max_idx = -1; > > + > > + /* Check we have already set targets */ > > + if (target_impl_cpu_num) > > + return; > > + > > + do { > > + arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_DISCOVER_IMPL_CPUS_FUNC_ID, > > + index, &res); > > + if (res.a0 == SMCCC_RET_NOT_SUPPORTED) > > + return; > > Can't you probe for this as part of the KVM guest services? +1, this needs to be predicated on actually detecting the hypervisor as KVM. > > + > > + if (max_idx < 0) { > > + /* res.a0 should have a valid maximum CPU implementation index */ > > + if (res.a0 >= MAX_TARGET_IMPL_CPUS) > > + return; > > + max_idx = res.a0; > > + } > > + > > + target_impl_cpus[index].midr = res.a1; > > + target_impl_cpus[index].revidr = res.a2; > > + index++; > > + } while (index <= max_idx); > > + > > + target_impl_cpu_num = index; > > + pr_info("Number of target implementation CPUs is %d\n", target_impl_cpu_num); > > +} > > + > > int __init pv_time_init(void) > > { > > int ret; > > Independent of this, I wonder what we should output in sysfs > (/sys/devices/system/cpu/cpu*/regs/identification/*). It's a bit crap, but maybe implementation index 0 gets reported through the 'main' midr/revidr files, otherwise have a directory per implementation index of midr/revidr. -- Thanks, Oliver