From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Bjorn Andersson <andersson@kernel.org>,
Christoffer Dall <christoffer.dall@arm.com>,
Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com>,
Chase Conklin <chase.conklin@arm.com>,
Eric Auger <eauger@redhat.com>
Subject: Re: [PATCH v2 01/12] KVM: arm64: nv: Add handling of EL2-specific timer registers
Date: Fri, 20 Dec 2024 17:38:28 -0800 [thread overview]
Message-ID: <Z2Yb8BWnqpt441V-@linux.dev> (raw)
In-Reply-To: <20241217142321.763801-2-maz@kernel.org>
On Tue, Dec 17, 2024 at 02:23:09PM +0000, Marc Zyngier wrote:
> @@ -3879,9 +4020,11 @@ static const struct sys_reg_desc cp15_64_regs[] = {
> { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
> { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
> { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
> + { SYS_DESC(SYS_AARCH32_CNTVCT), access_arch_timer },
> { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
> { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
> { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
> + { SYS_DESC(SYS_AARCH32_CNTVCTSS), access_arch_timer },
> };
Huh. You know, I had always thought we hid 32-bit EL0 from nested
guests, but I now realize that isn't the case. Of course, we don't have
the necessary trap reflection for exits that came out of a 32-bit EL0,
nor should we bother.
Of the 4 NV2 implementations I'm aware of (Neoverse-V1, Neoverse-V2,
AmpereOne, M2) only Neoverse-V1 supports 32-bit userspace. And even
then, a lot of deployments of V1 have a broken NV2 implementation.
What do you think about advertising a 64-bit only EL0 for nested VMs?
--
Thanks,
Oliver
next prev parent reply other threads:[~2024-12-21 1:40 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-17 14:23 [PATCH v2 00/12] KVM: arm64: Add NV timer support Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 01/12] KVM: arm64: nv: Add handling of EL2-specific timer registers Marc Zyngier
2024-12-21 1:38 ` Oliver Upton [this message]
2024-12-21 9:57 ` Marc Zyngier
2024-12-21 21:58 ` Oliver Upton
2024-12-17 14:23 ` [PATCH v2 02/12] KVM: arm64: nv: Sync nested timer state with FEAT_NV2 Marc Zyngier
2025-01-06 2:19 ` Wei-Lin Chang
2025-01-26 15:25 ` Volodymyr Babchuk
2025-01-27 17:15 ` Marc Zyngier
2025-01-28 11:29 ` Volodymyr Babchuk
2025-01-28 12:17 ` Marc Zyngier
2025-01-28 13:56 ` Volodymyr Babchuk
2024-12-17 14:23 ` [PATCH v2 03/12] KVM: arm64: nv: Publish emulated timer interrupt state in the in-memory state Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 04/12] KVM: arm64: nv: Use FEAT_ECV to trap access to EL0 timers Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 05/12] KVM: arm64: nv: Accelerate EL0 timer read accesses when FEAT_ECV in use Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 06/12] KVM: arm64: nv: Accelerate EL0 counter accesses from hypervisor context Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 07/12] KVM: arm64: Handle counter access early in non-HYP context Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 08/12] KVM: arm64: nv: Add trap routing for CNTHCTL_EL2.EL1{NVPCT,NVVCT,TVT,TVCT} Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 09/12] KVM: arm64: nv: Propagate CNTHCTL_EL2.EL1NV{P,V}CT bits Marc Zyngier
2025-01-06 2:33 ` Wei-Lin Chang
2025-01-17 15:19 ` Marc Zyngier
2025-01-21 6:04 ` Wei-Lin Chang
2024-12-17 14:23 ` [PATCH v2 10/12] KVM: arm64: nv: Sanitise CNTHCTL_EL2 Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 11/12] KVM: arm64: Work around x1e's CNTVOFF_EL2 bogosity Marc Zyngier
2024-12-17 14:23 ` [PATCH v2 12/12] KVM: arm64: nv: Document EL2 timer API Marc Zyngier
2025-01-02 19:15 ` [PATCH v2 00/12] KVM: arm64: Add NV timer support Oliver Upton
2025-01-02 19:25 ` Marc Zyngier
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