* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 18:16 ` [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Vincenzo Frascino
@ 2025-01-03 22:14 ` Rob Herring
2025-01-07 12:56 ` Jessica Clarke
2025-01-07 14:17 ` Vincenzo Frascino
2025-01-03 22:26 ` Rob Herring
2025-01-07 12:44 ` Jessica Clarke
2 siblings, 2 replies; 15+ messages in thread
From: Rob Herring @ 2025-01-03 22:14 UTC (permalink / raw)
To: Vincenzo Frascino
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Krzysztof Kozlowski, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Russell King
On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:
>
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
>
> Introduce morello.dtsi.
>
> Note: Morello fvp will be introduced with a future patch series.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/arm64/boot/dts/arm/morello.dtsi | 467 +++++++++++++++++++++++++++
> 1 file changed, 467 insertions(+)
> create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
>
> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
> new file mode 100644
> index 000000000000..0089b4f2eca7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/morello.dtsi
> @@ -0,0 +1,467 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
Drop this container node.
> + soc_refclk50mhz: clock-50000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_pclk";
> + };
> +
> + soc_uartclk: clock-50000000-uart {
There's little point to having 2 fixed clocks with no s/w controls at
the same frequency. Drop.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "uartclk";
> + };
> +
> + soc_refclk85mhz: clock-85000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <85000000>;
> + clock-output-names = "iofpga:aclk";
> + };
> +
> + dpu_aclk: clock-350000000 {
> + /* 77.1 MHz derived from 24 MHz reference clock */
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <350000000>;
> + clock-output-names = "aclk";
> + };
> +
> + dpu_pixel_clk: clock-148500000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <148500000>;
> + clock-output-names = "pxclk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,neoverse-n1";
I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
"arm,neoverse-n1-morello" if we want to capture what it is derived
from and since "arm,morello" is taken already.
> + reg = <0x0 0x0>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_0>;
> + clocks = <&scmi_dvfs 0>;
> +
> + l2_0: l2-cache-0 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x100000>;
> + cache-unified;
> + };
> + };
> + };
> +
> + cpu1: cpu@100 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x100>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_1>;
> + clocks = <&scmi_dvfs 0>;
> +
> + l2_1: l2-cache-1 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> +
> + cpu2: cpu@10000 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x10000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_2>;
> + clocks = <&scmi_dvfs 1>;
> +
> + l2_2: l2-cache-2 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> +
> + cpu3: cpu@10100 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x10100>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_3>;
> + clocks = <&scmi_dvfs 1>;
> +
> + l2_3: l2-cache-3 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> + };
> +
> + firmware {
> + interrupt-parent = <&gic>;
> +
> + scmi {
> + compatible = "arm,scmi";
> + mbox-names = "tx", "rx";
> + mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
> + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + scmi_dvfs: protocol@13 {
> + reg = <0x13>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> + };
> + };
> +
> + /* The first bank of memory, memory map is actually provided by UEFI. */
> + memory@80000000 {
> + device_type = "memory";
> + /* [0x80000000-0xffffffff] */
> + reg = <0x00000000 0x80000000 0x0 0x7f000000>;
> + };
> +
> + memory@8080000000 {
> + device_type = "memory";
> + /* [0x8080000000-0x83f7ffffff] */
> + reg = <0x00000080 0x80000000 0x3 0x78000000>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
Missing the CPU specific compatible.
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure-firmware@ff000000 {
> + reg = <0x0 0xff000000 0x0 0x01000000>;
> + no-map;
> + };
> + };
> +
> + spe-pmu {
> + compatible = "arm,statistical-profiling-extension-v1";
> + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + dp0: display@2cc00000 {
Sort nodes by address.
> + compatible = "arm,mali-d32", "arm,mali-d71";
> + reg = <0x0 0x2cc00000 0x0 0x20000>;
> + interrupts = <0 69 4>;
> + clocks = <&dpu_aclk>;
> + clock-names = "aclk";
> + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
> + <&smmu_dp 8>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pl0: pipeline@0 {
> + reg = <0>;
> + clocks = <&dpu_pixel_clk>;
> + clock-names = "pxclk";
> + port {
> + dp_pl0_out0: endpoint {
> + remote-endpoint = <&tda998x_0_input>;
> + };
> + };
> + };
> + };
> +
> + i2c0: i2c@1c0f0000 {
> + compatible = "cdns,i2c-r1p14";
> + reg = <0x0 0x1c0f0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dpu_aclk>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + hdmi_tx: hdmi-transmitter@70 {
> + compatible = "nxp,tda998x";
> + reg = <0x70>;
> + video-ports = <0x234501>;
> + port {
> + tda998x_0_input: endpoint {
> + remote-endpoint = <&dp_pl0_out0>;
> + };
> + };
> + };
> + };
> +
> + gic: interrupt-controller@2c010000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
> + <0x0 0x300c0000 0x0 0x80000>; /* GICR */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #interrupt-cells = <3>;
> + interrupt-controller;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + its1: msi-controller@30040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30040000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its2: msi-controller@30060000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30060000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its_ccix: msi-controller@30080000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30080000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its_pcie: msi-controller@300a0000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x300a0000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + smmu_dp: iommu@2ce00000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x2ce00000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "cmdq-sync";
> + #iommu-cells = <1>;
> + };
> +
> + smmu_ccix: iommu@4f000000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x4f000000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + msi-parent = <&its1 0>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> + smmu_pcie: iommu@4f400000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x4f400000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + msi-parent = <&its2 0>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> + mailbox: mhu@45000000 {
> + compatible = "arm,mhu-doorbell", "arm,primecell";
> + reg = <0x0 0x45000000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + clocks = <&soc_refclk50mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + pcie_ctlr: pcie@28c0000000 {
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + reg = <0x28 0xC0000000 0 0x10000000>;
> + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
> + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
> + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
> + bus-range = <0 255>;
Not needed unless less than this range.
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
> + msi-map = <0 &its_pcie 0 0x10000>;
> + iommu-map = <0 &smmu_pcie 0 0x10000>;
> + };
> +
> + ccix_pcie_ctlr: pcie@4fc0000000 {
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + reg = <0x4f 0xC0000000 0 0x10000000>;
> + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>,
> + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>,
> + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>;
> + bus-range = <0 255>;
> + linux,pci-domain = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
> + msi-map = <0 &its_ccix 0 0x10000>;
> + iommu-map = <0 &smmu_ccix 0 0x10000>;
> + };
> +
> + uart0: serial@2a400000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0 0x2a400000 0x0 0x1000>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
> + clock-names = "uartclk", "apb_pclk";
> +
> + status = "disabled";
> + };
> +
> + sram: sram@45200000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x06000000 0x0 0x8000>;
> + ranges = <0 0x0 0x06000000 0x8000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_scp_hpri0: scp-sram@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x80>;
> + };
> +
> + cpu_scp_hpri1: scp-sram@80 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x80 0x80>;
> + };
> + };
> +
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 22:14 ` Rob Herring
@ 2025-01-07 12:56 ` Jessica Clarke
2025-01-07 14:34 ` Vincenzo Frascino
2025-01-07 14:17 ` Vincenzo Frascino
1 sibling, 1 reply; 15+ messages in thread
From: Jessica Clarke @ 2025-01-07 12:56 UTC (permalink / raw)
To: Rob Herring
Cc: Vincenzo Frascino, devicetree, linux-kernel, linux-arm-kernel,
Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Russell King
On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote:
> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
> <vincenzo.frascino@arm.com> wrote:
> > + cpus {
> > + #address-cells = <2>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,neoverse-n1";
>
> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
> "arm,neoverse-n1-morello" if we want to capture what it is derived
> from and since "arm,morello" is taken already.
Rainier is the codename of the core itself, and Morello LLVM recognises
-mcpu=rainier not -mcpu=morello (there's -march=morello instead), so
perhaps it should really be "arm,rainier". Though SMBIOS reports it as
Morello-R0P1 so it may be best to use "arm,morello" here.
The real problem is that the board compatible has changed to include a
generic "arm,morello" node, with the argument that a v2 board could
appear. So why not instead change *that* to be something like:
compatible = "arm,morello-sdp-v1", "arm,morello-sdp";
Then you can use "arm,morello" here for the cores.
Though some of this may depend on what the FVP's DTS looks like; is it
going to claim to be a Morello SDP, or does there need to be a common
denominator compatible beneath that it can use?
Please CC me on future versions of this series.
Jess
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-07 12:56 ` Jessica Clarke
@ 2025-01-07 14:34 ` Vincenzo Frascino
2025-01-07 14:51 ` Jessica Clarke
0 siblings, 1 reply; 15+ messages in thread
From: Vincenzo Frascino @ 2025-01-07 14:34 UTC (permalink / raw)
To: Jessica Clarke, Rob Herring
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Krzysztof Kozlowski, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Russell King
Hi Jessica,
Thank you for your review.
On 07/01/2025 12:56, Jessica Clarke wrote:
> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote:
>> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
>> <vincenzo.frascino@arm.com> wrote:
>>> + cpus {
>>> + #address-cells = <2>;
>>> + #size-cells = <0>;
>>> +
>>> + cpu0: cpu@0 {
>>> + compatible = "arm,neoverse-n1";
>>
>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
>> "arm,neoverse-n1-morello" if we want to capture what it is derived
>> from and since "arm,morello" is taken already.
>
> Rainier is the codename of the core itself, and Morello LLVM recognises
> -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so
> perhaps it should really be "arm,rainier". Though SMBIOS reports it as
> Morello-R0P1 so it may be best to use "arm,morello" here.
>
We agree on the concept. It should either be "arm,rainier" or "arm,morello-r0p1"
if we want to capture the information of SMBIOS. When we reach consensus I will
update the patches accordingly (Please have a look at my reply to Rob).
> The real problem is that the board compatible has changed to include a
> generic "arm,morello" node, with the argument that a v2 board could
> appear. So why not instead change *that* to be something like:
>
> compatible = "arm,morello-sdp-v1", "arm,morello-sdp";
>
> Then you can use "arm,morello" here for the cores.>
The name morello on its own is too overloaded of meaning if we do not specify to
what we are referring to.
> Though some of this may depend on what the FVP's DTS looks like; is it
> going to claim to be a Morello SDP, or does there need to be a common
> denominator compatible beneath that it can use?
>
I still did not start bringing up to speed the DTS for FVP but I think that we
should distinguish in between SDP and FVP since not everything is the same,
hence it should have something similar to:
compatible = "arm,morello-fvp", "arm,morello";
> Please CC me on future versions of this series.
>
Will do.
> Jess
--
Regards,
Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-07 14:34 ` Vincenzo Frascino
@ 2025-01-07 14:51 ` Jessica Clarke
2025-01-07 14:56 ` Vincenzo Frascino
0 siblings, 1 reply; 15+ messages in thread
From: Jessica Clarke @ 2025-01-07 14:51 UTC (permalink / raw)
To: Vincenzo Frascino
Cc: Rob Herring, devicetree, linux-kernel, linux-arm-kernel,
Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Russell King
On 7 Jan 2025, at 14:34, Vincenzo Frascino <vincenzo.frascino@arm.com> wrote:
>
> Hi Jessica,
>
> Thank you for your review.
>
> On 07/01/2025 12:56, Jessica Clarke wrote:
>> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote:
>>> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
>>> <vincenzo.frascino@arm.com> wrote:
>>>> + cpus {
>>>> + #address-cells = <2>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + cpu0: cpu@0 {
>>>> + compatible = "arm,neoverse-n1";
>>>
>>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
>>> "arm,neoverse-n1-morello" if we want to capture what it is derived
>>> from and since "arm,morello" is taken already.
>>
>> Rainier is the codename of the core itself, and Morello LLVM recognises
>> -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so
>> perhaps it should really be "arm,rainier". Though SMBIOS reports it as
>> Morello-R0P1 so it may be best to use "arm,morello" here.
>>
>
> We agree on the concept. It should either be "arm,rainier" or "arm,morello-r0p1"
r0p1 isn’t right. Boards with r0p0 and r0p2 CPUs also exist (although
the former are now only within Arm, but the latter are in the wild in
limited numbers, including a couple here at Cambridge).
> if we want to capture the information of SMBIOS. When we reach consensus I will
> update the patches accordingly (Please have a look at my reply to Rob).
>
>> The real problem is that the board compatible has changed to include a
>> generic "arm,morello" node, with the argument that a v2 board could
>> appear. So why not instead change *that* to be something like:
>>
>> compatible = "arm,morello-sdp-v1", "arm,morello-sdp";
>>
>> Then you can use "arm,morello" here for the cores.>
>
> The name morello on its own is too overloaded of meaning if we do not specify to
> what we are referring to.
>
>> Though some of this may depend on what the FVP's DTS looks like; is it
>> going to claim to be a Morello SDP, or does there need to be a common
>> denominator compatible beneath that it can use?
>>
>
> I still did not start bringing up to speed the DTS for FVP but I think that we
> should distinguish in between SDP and FVP since not everything is the same,
> hence it should have something similar to:
>
> compatible = "arm,morello-fvp", "arm,morello";
>
>> Please CC me on future versions of this series.
>>
>
> Will do.
>
>> Jess
>
> --
> Regards,
> Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-07 14:51 ` Jessica Clarke
@ 2025-01-07 14:56 ` Vincenzo Frascino
0 siblings, 0 replies; 15+ messages in thread
From: Vincenzo Frascino @ 2025-01-07 14:56 UTC (permalink / raw)
To: Jessica Clarke
Cc: Rob Herring, devicetree, linux-kernel, linux-arm-kernel,
Linus Walleij, Krzysztof Kozlowski, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Russell King
On 07/01/2025 14:51, Jessica Clarke wrote:
> On 7 Jan 2025, at 14:34, Vincenzo Frascino <vincenzo.frascino@arm.com> wrote:
>>
>> Hi Jessica,
>>
>> Thank you for your review.
>>
>> On 07/01/2025 12:56, Jessica Clarke wrote:
>>> On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote:
>>>> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
>>>> <vincenzo.frascino@arm.com> wrote:
>>>>> + cpus {
>>>>> + #address-cells = <2>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + cpu0: cpu@0 {
>>>>> + compatible = "arm,neoverse-n1";
>>>>
>>>> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
>>>> "arm,neoverse-n1-morello" if we want to capture what it is derived
>>>> from and since "arm,morello" is taken already.
>>>
>>> Rainier is the codename of the core itself, and Morello LLVM recognises
>>> -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so
>>> perhaps it should really be "arm,rainier". Though SMBIOS reports it as
>>> Morello-R0P1 so it may be best to use "arm,morello" here.
>>>
>>
>> We agree on the concept. It should either be "arm,rainier" or "arm,morello-r0p1"
>
> r0p1 isn’t right. Boards with r0p0 and r0p2 CPUs also exist (although
> the former are now only within Arm, but the latter are in the wild in
> limited numbers, including a couple here at Cambridge).
>
Agreed, my proposals were in order of preference. "arm,rainier" seems the best
choice. Let's see what Rob thinks.
[...]
--
Regards,
Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 22:14 ` Rob Herring
2025-01-07 12:56 ` Jessica Clarke
@ 2025-01-07 14:17 ` Vincenzo Frascino
1 sibling, 0 replies; 15+ messages in thread
From: Vincenzo Frascino @ 2025-01-07 14:17 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Krzysztof Kozlowski, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Russell King
Hi Rob,
Happy new year!
On 03/01/2025 22:14, Rob Herring wrote:
> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
> <vincenzo.frascino@arm.com> wrote:
>>
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
>> some functionalities that have conveniently been included in
>> morello.dtsi to avoid duplication.
>>
>> Introduce morello.dtsi.
>>
>> Note: Morello fvp will be introduced with a future patch series.
>>
>> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
>> ---
>> arch/arm64/boot/dts/arm/morello.dtsi | 467 +++++++++++++++++++++++++++
>> 1 file changed, 467 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
>> new file mode 100644
>> index 000000000000..0089b4f2eca7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/arm/morello.dtsi
>> @@ -0,0 +1,467 @@
>> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
>> +/*
>> + * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + interrupt-parent = <&gic>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + clocks {
>
> Drop this container node.
>
Will do in v5.
>> + soc_refclk50mhz: clock-50000000 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <50000000>;
>> + clock-output-names = "apb_pclk";
>> + };
>> +
>> + soc_uartclk: clock-50000000-uart {
>
> There's little point to having 2 fixed clocks with no s/w controls at
> the same frequency. Drop.
>
Ok, will use the same reference for both.
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <50000000>;
>> + clock-output-names = "uartclk";
>> + };
>> +
>> + soc_refclk85mhz: clock-85000000 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <85000000>;
>> + clock-output-names = "iofpga:aclk";
>> + };
>> +
>> + dpu_aclk: clock-350000000 {
>> + /* 77.1 MHz derived from 24 MHz reference clock */
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <350000000>;
>> + clock-output-names = "aclk";
>> + };
>> +
>> + dpu_pixel_clk: clock-148500000 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <148500000>;
>> + clock-output-names = "pxclk";
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + compatible = "arm,neoverse-n1";
>
> I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps
> "arm,neoverse-n1-morello" if we want to capture what it is derived
> from and since "arm,morello" is taken already.
>
Thank you for this, is the type of feedback I was looking for. My interpretation
of "compatible" was that it is the common denominator in between in between two
or more elements (hence I used neoverse-n1), but clearly it was a bit off.
Since the CPU core is called Rainier, we could either use "arm,ranier" or
"arm,morello-r0p1" to be in line with the SMBIOS.
What do you think?
[...]
>> +
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
>
> Missing the CPU specific compatible.
>
I will add it in v5.
[...]
>> +
>> + soc: soc {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-parent = <&gic>;
>> + ranges;
>> +
>> + dp0: display@2cc00000 {
>
> Sort nodes by address.
>
Ok, I will do in v5.
[...]
>> + pcie_ctlr: pcie@28c0000000 {
>> + device_type = "pci";
>> + compatible = "pci-host-ecam-generic";
>> + reg = <0x28 0xC0000000 0 0x10000000>;
>> + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
>> + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
>> + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
>> + bus-range = <0 255>;
>
> Not needed unless less than this range.
>
Ok, I will remove it in v5.
[...]
--
Regards,
Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 18:16 ` [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Vincenzo Frascino
2025-01-03 22:14 ` Rob Herring
@ 2025-01-03 22:26 ` Rob Herring
2025-01-07 14:41 ` Vincenzo Frascino
2025-01-07 12:44 ` Jessica Clarke
2 siblings, 1 reply; 15+ messages in thread
From: Rob Herring @ 2025-01-03 22:26 UTC (permalink / raw)
To: Vincenzo Frascino
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Krzysztof Kozlowski, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Russell King
On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:
>
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
One more thing...
> + i2c0: i2c@1c0f0000 {
> + compatible = "cdns,i2c-r1p14";
> + reg = <0x0 0x1c0f0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dpu_aclk>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + hdmi_tx: hdmi-transmitter@70 {
> + compatible = "nxp,tda998x";
It is odd that you add this node here, but don't enable i2c. If this
is shared with fvp, then enable i2c here. If it isn't, then move this
to the soc/sdb .dts.
I'd rather see the FVP dts now rather than later so we can review how
you split things. It's a little odd not being soc.dtsi and board.dts,
but that's fine I think.
> + reg = <0x70>;
> + video-ports = <0x234501>;
> + port {
> + tda998x_0_input: endpoint {
> + remote-endpoint = <&dp_pl0_out0>;
> + };
> + };
> + };
> + };
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 22:26 ` Rob Herring
@ 2025-01-07 14:41 ` Vincenzo Frascino
0 siblings, 0 replies; 15+ messages in thread
From: Vincenzo Frascino @ 2025-01-07 14:41 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Krzysztof Kozlowski, Conor Dooley, Liviu Dudau, Sudeep Holla,
Lorenzo Pieralisi, Russell King
On 03/01/2025 22:26, Rob Herring wrote:
> On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino
> <vincenzo.frascino@arm.com> wrote:
>>
>> The Morello architecture is an experimental extension to Armv8.2-A,
>> which extends the AArch64 state with the principles proposed in
>> version 7 of the Capability Hardware Enhanced RISC Instructions
>> (CHERI) ISA.
>>
>> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
>> some functionalities that have conveniently been included in
>> morello.dtsi to avoid duplication.
>
> One more thing...
>
>> + i2c0: i2c@1c0f0000 {
>> + compatible = "cdns,i2c-r1p14";
>> + reg = <0x0 0x1c0f0000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&dpu_aclk>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + hdmi_tx: hdmi-transmitter@70 {
>> + compatible = "nxp,tda998x";
>
> It is odd that you add this node here, but don't enable i2c. If this
> is shared with fvp, then enable i2c here. If it isn't, then move this
> to the soc/sdb .dts.
>
This node should be on the dts file. I had it there in v2 and I can't recall the
rationale for which I moved it here. It is clearly wrong. I will move it back in
v5.
> I'd rather see the FVP dts now rather than later so we can review how
> you split things. It's a little odd not being soc.dtsi and board.dts,
> but that's fine I think.
I do not have a complete DTS for FVP yet (I was planning to work on after this
series is merged). Is it OK if I post it with a future series and we move things
around at that stage if there is a need?
>
>> + reg = <0x70>;
>> + video-ports = <0x234501>;
>> + port {
>> + tda998x_0_input: endpoint {
>> + remote-endpoint = <&dp_pl0_out0>;
>> + };
>> + };
>> + };
>> + };
--
Regards,
Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-03 18:16 ` [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Vincenzo Frascino
2025-01-03 22:14 ` Rob Herring
2025-01-03 22:26 ` Rob Herring
@ 2025-01-07 12:44 ` Jessica Clarke
2025-01-07 14:49 ` Vincenzo Frascino
2 siblings, 1 reply; 15+ messages in thread
From: Jessica Clarke @ 2025-01-07 12:44 UTC (permalink / raw)
To: Vincenzo Frascino
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Russell King
On Fri, Jan 03, 2025 at 06:16:21PM +0000, Vincenzo Frascino wrote:
> The Morello architecture is an experimental extension to Armv8.2-A,
> which extends the AArch64 state with the principles proposed in
> version 7 of the Capability Hardware Enhanced RISC Instructions
> (CHERI) ISA.
>
> The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share
> some functionalities that have conveniently been included in
> morello.dtsi to avoid duplication.
>
> Introduce morello.dtsi.
>
> Note: Morello fvp will be introduced with a future patch series.
>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/arm64/boot/dts/arm/morello.dtsi | 467 +++++++++++++++++++++++++++
> 1 file changed, 467 insertions(+)
> create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi
>
> diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm/morello.dtsi
> new file mode 100644
> index 000000000000..0089b4f2eca7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/arm/morello.dtsi
> @@ -0,0 +1,467 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
> +/*
> + * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clocks {
> + soc_refclk50mhz: clock-50000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "apb_pclk";
> + };
> +
> + soc_uartclk: clock-50000000-uart {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "uartclk";
> + };
> +
> + soc_refclk85mhz: clock-85000000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <85000000>;
> + clock-output-names = "iofpga:aclk";
If this is ACLK for the IOFPGA outside the SoC, why is it called soc_refclk85mhz?
Not that it seems to be used in this patch series.
> + };
> +
> + dpu_aclk: clock-350000000 {
> + /* 77.1 MHz derived from 24 MHz reference clock */
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <350000000>;
> + clock-output-names = "aclk";
> + };
> +
> + dpu_pixel_clk: clock-148500000 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <148500000>;
> + clock-output-names = "pxclk";
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x0>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_0>;
> + clocks = <&scmi_dvfs 0>;
> +
> + l2_0: l2-cache-0 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> +
> + l3_0: l3-cache {
> + compatible = "cache";
> + cache-level = <3>;
> + cache-size = <0x100000>;
> + cache-unified;
> + };
> + };
> + };
> +
> + cpu1: cpu@100 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x100>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_1>;
> + clocks = <&scmi_dvfs 0>;
> +
> + l2_1: l2-cache-1 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> +
> + cpu2: cpu@10000 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x10000>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_2>;
> + clocks = <&scmi_dvfs 1>;
> +
> + l2_2: l2-cache-2 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> +
> + cpu3: cpu@10100 {
> + compatible = "arm,neoverse-n1";
> + reg = <0x0 0x10100>;
> + device_type = "cpu";
> + enable-method = "psci";
> + /* 4 ways set associative */
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <512>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <512>;
> + next-level-cache = <&l2_3>;
> + clocks = <&scmi_dvfs 1>;
> +
> + l2_3: l2-cache-3 {
> + compatible = "cache";
> + cache-level = <2>;
> + /* 8 ways set associative */
> + cache-size = <0x100000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + cache-unified;
> + next-level-cache = <&l3_0>;
> + };
> + };
> + };
> +
> + firmware {
> + interrupt-parent = <&gic>;
> +
> + scmi {
> + compatible = "arm,scmi";
> + mbox-names = "tx", "rx";
> + mboxes = <&mailbox 1 0>, <&mailbox 1 1>;
> + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + scmi_dvfs: protocol@13 {
> + reg = <0x13>;
> + #clock-cells = <1>;
> + };
> +
> + scmi_clk: protocol@14 {
> + reg = <0x14>;
> + #clock-cells = <1>;
> + };
> + };
> + };
> +
> + /* The first bank of memory, memory map is actually provided by UEFI. */
> + memory@80000000 {
> + device_type = "memory";
> + /* [0x80000000-0xffffffff] */
> + reg = <0x00000000 0x80000000 0x0 0x7f000000>;
> + };
> +
> + memory@8080000000 {
> + device_type = "memory";
> + /* [0x8080000000-0x83f7ffffff] */
> + reg = <0x00000080 0x80000000 0x3 0x78000000>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure-firmware@ff000000 {
> + reg = <0x0 0xff000000 0x0 0x01000000>;
> + no-map;
> + };
> + };
> +
> + spe-pmu {
> + compatible = "arm,statistical-profiling-extension-v1";
> + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + dp0: display@2cc00000 {
> + compatible = "arm,mali-d32", "arm,mali-d71";
> + reg = <0x0 0x2cc00000 0x0 0x20000>;
> + interrupts = <0 69 4>;
> + clocks = <&dpu_aclk>;
> + clock-names = "aclk";
> + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>,
> + <&smmu_dp 8>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pl0: pipeline@0 {
> + reg = <0>;
> + clocks = <&dpu_pixel_clk>;
> + clock-names = "pxclk";
> + port {
> + dp_pl0_out0: endpoint {
> + remote-endpoint = <&tda998x_0_input>;
> + };
> + };
> + };
> + };
> +
> + i2c0: i2c@1c0f0000 {
The I2C controller lives in the IOFGPA on the board, not the SoC.
> + compatible = "cdns,i2c-r1p14";
> + reg = <0x0 0x1c0f0000 0x0 0x1000>;
> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&dpu_aclk>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + hdmi_tx: hdmi-transmitter@70 {
The transmitter is a discrete chip on the board, not the SoC.
Jess
> + compatible = "nxp,tda998x";
> + reg = <0x70>;
> + video-ports = <0x234501>;
> + port {
> + tda998x_0_input: endpoint {
> + remote-endpoint = <&dp_pl0_out0>;
> + };
> + };
> + };
> + };
> +
> + gic: interrupt-controller@2c010000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */
> + <0x0 0x300c0000 0x0 0x80000>; /* GICR */
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #interrupt-cells = <3>;
> + interrupt-controller;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + its1: msi-controller@30040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30040000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its2: msi-controller@30060000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30060000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its_ccix: msi-controller@30080000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x30080000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> +
> + its_pcie: msi-controller@300a0000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x300a0000 0x0 0x20000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };
> +
> + smmu_dp: iommu@2ce00000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x2ce00000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "cmdq-sync";
> + #iommu-cells = <1>;
> + };
> +
> + smmu_ccix: iommu@4f000000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x4f000000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + msi-parent = <&its1 0>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> + smmu_pcie: iommu@4f400000 {
> + compatible = "arm,smmu-v3";
> + reg = <0x0 0x4f400000 0x0 0x40000>;
> +
> + interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
> + msi-parent = <&its2 0>;
> + #iommu-cells = <1>;
> + dma-coherent;
> + };
> +
> + mailbox: mhu@45000000 {
> + compatible = "arm,mhu-doorbell", "arm,primecell";
> + reg = <0x0 0x45000000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <2>;
> + clocks = <&soc_refclk50mhz>;
> + clock-names = "apb_pclk";
> + };
> +
> + pcie_ctlr: pcie@28c0000000 {
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + reg = <0x28 0xC0000000 0 0x10000000>;
> + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>,
> + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>,
> + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>;
> + bus-range = <0 255>;
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
> + msi-map = <0 &its_pcie 0 0x10000>;
> + iommu-map = <0 &smmu_pcie 0 0x10000>;
> + };
> +
> + ccix_pcie_ctlr: pcie@4fc0000000 {
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + reg = <0x4f 0xC0000000 0 0x10000000>;
> + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>,
> + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>,
> + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>;
> + bus-range = <0 255>;
> + linux,pci-domain = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + dma-coherent;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
> + msi-map = <0 &its_ccix 0 0x10000>;
> + iommu-map = <0 &smmu_ccix 0 0x10000>;
> + };
> +
> + uart0: serial@2a400000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0x0 0x2a400000 0x0 0x1000>;
> + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&soc_uartclk>, <&soc_refclk50mhz>;
> + clock-names = "uartclk", "apb_pclk";
> +
> + status = "disabled";
> + };
> +
> + sram: sram@45200000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x06000000 0x0 0x8000>;
> + ranges = <0 0x0 0x06000000 0x8000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpu_scp_hpri0: scp-sram@0 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x0 0x80>;
> + };
> +
> + cpu_scp_hpri1: scp-sram@80 {
> + compatible = "arm,scmi-shmem";
> + reg = <0x80 0x80>;
> + };
> + };
> +
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities
2025-01-07 12:44 ` Jessica Clarke
@ 2025-01-07 14:49 ` Vincenzo Frascino
0 siblings, 0 replies; 15+ messages in thread
From: Vincenzo Frascino @ 2025-01-07 14:49 UTC (permalink / raw)
To: Jessica Clarke
Cc: devicetree, linux-kernel, linux-arm-kernel, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Liviu Dudau,
Sudeep Holla, Lorenzo Pieralisi, Russell King
[...]
>> +
>> + soc_refclk85mhz: clock-85000000 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <85000000>;
>> + clock-output-names = "iofpga:aclk";
>
> If this is ACLK for the IOFPGA outside the SoC, why is it called soc_refclk85mhz?
>
> Not that it seems to be used in this patch series.
>
Good catch.
Indeed, it is not used in this series and the name and placement are incorrect.
I can either rename it and move it to the board file or remove it and add it
again in future.
[...]
>> +
>> + i2c0: i2c@1c0f0000 {
>
> The I2C controller lives in the IOFGPA on the board, not the SoC.
>
>> + compatible = "cdns,i2c-r1p14";
>> + reg = <0x0 0x1c0f0000 0x0 0x1000>;
>> + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&dpu_aclk>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + hdmi_tx: hdmi-transmitter@70 {
>
> The transmitter is a discrete chip on the board, not the SoC.
>
Agreed on both the points, please have a look at my reply to Rob.
> Jess
[...]
--
Regards,
Vincenzo
^ permalink raw reply [flat|nested] 15+ messages in thread