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Tue, 07 Jan 2025 04:56:15 -0800 (PST) Received: from Jessicas-MacBook-Pro.localdomain ([131.111.5.201]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-436611ea487sm593720325e9.8.2025.01.07.04.56.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Jan 2025 04:56:15 -0800 (PST) Received: by Jessicas-MacBook-Pro.localdomain (Postfix, from userid 501) id B3086CDDDC3E; Tue, 7 Jan 2025 12:56:14 +0000 (GMT) Date: Tue, 7 Jan 2025 12:56:14 +0000 From: Jessica Clarke To: Rob Herring Cc: Vincenzo Frascino , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Linus Walleij , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King Subject: Re: [PATCH v4 2/4] arm64: dts: morello: Add support for common functionalities Message-ID: References: <20250103181623.1980433-1-vincenzo.frascino@arm.com> <20250103181623.1980433-3-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250107_045617_414713_D5D2EC04 X-CRM114-Status: GOOD ( 17.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jan 03, 2025 at 04:14:31PM -0600, Rob Herring wrote: > On Fri, Jan 3, 2025 at 12:16 PM Vincenzo Frascino > wrote: > > + cpus { > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "arm,neoverse-n1"; > > I'm pretty sure the N1 doesn't support CHERI/morello. Perhaps > "arm,neoverse-n1-morello" if we want to capture what it is derived > from and since "arm,morello" is taken already. Rainier is the codename of the core itself, and Morello LLVM recognises -mcpu=rainier not -mcpu=morello (there's -march=morello instead), so perhaps it should really be "arm,rainier". Though SMBIOS reports it as Morello-R0P1 so it may be best to use "arm,morello" here. The real problem is that the board compatible has changed to include a generic "arm,morello" node, with the argument that a v2 board could appear. So why not instead change *that* to be something like: compatible = "arm,morello-sdp-v1", "arm,morello-sdp"; Then you can use "arm,morello" here for the cores. Though some of this may depend on what the FVP's DTS looks like; is it going to claim to be a Morello SDP, or does there need to be a common denominator compatible beneath that it can use? Please CC me on future versions of this series. Jess