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Received: from authenticated user by stravinsky.debian.org with esmtpsa (TLS1.3:ECDHE_SECP256R1__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.94.2) (envelope-from ) id 1tS5Or-005cYz-TA; Mon, 30 Dec 2024 02:20:58 +0000 Date: Mon, 30 Dec 2024 03:20:55 +0100 From: Chris Hofstaedtler To: Heiko Stuebner Cc: andy.yan@rock-chips.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andrzej.hajda@intel.com, neil.armstrong@linaro.org, rfoss@kernel.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@gmail.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, quentin.schulz@cherry.de, Heiko Stuebner , Daniel Semkowicz , Dmitry Yashin Subject: Re: [PATCH v4 1/3] drm/bridge/synopsys: Add MIPI DSI2 host controller bridge Message-ID: References: <20241209231021.2180582-1-heiko@sntech.de> <20241209231021.2180582-2-heiko@sntech.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20241209231021.2180582-2-heiko@sntech.de> X-Debian-User: zeha X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241229_182132_359539_0F04996A X-CRM114-Status: GOOD ( 15.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Tue, Dec 10, 2024 at 12:10:19AM +0100, Heiko Stuebner wrote: > From: Heiko Stuebner > > Add a Synopsys Designware MIPI DSI host DRM bridge driver for their > DSI2 host controller, based on the Rockchip version from the driver > rockchip/dw-mipi-dsi2.c in their vendor-kernel with phy & bridge APIs. > > While the driver is heavily modelled after the previous IP, the register > set of this DSI2 controller is completely different and there are also > additional properties like the variable-width phy interface. > > Tested-by: Daniel Semkowicz > Tested-by: Dmitry Yashin > Reviewed-by: Neil Armstrong > Signed-off-by: Heiko Stuebner [..] > +static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) > +{ > + u32 val = 0, mode; > + int ret; > + > + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) > + val |= BLK_HFP_HS_EN; > + > + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) > + val |= BLK_HBP_HS_EN; > + > + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) > + val |= BLK_HSA_HS_EN; For all three of these: is setting an ENable bit the right thing to turn features *off*? > + if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) > + val |= VID_MODE_TYPE_BURST; > + else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) > + val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; > + else > + val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; > + > + regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val); > + > + regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE); > + ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, > + mode, mode & VIDEO_MODE, > + 1000, MODE_STATUS_TIMEOUT_US); > + if (ret < 0) > + dev_err(dsi2->dev, "failed to enter video mode\n"); > +} ... Chris