[PATCH] ARM: cacheinfo fix format field mask

[PATCH] ARM: cacheinfo fix format field mask

[Dmitry Baryshkov]

Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.

Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm/kernel/cacheinfo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/kernel/cacheinfo.c b/arch/arm/kernel/cacheinfo.c
index a8eabcaa18d8941ce31ad267ce0d369b8d53886a..e1469b6417804d2802e847031950cb99b7b4e1d2 100644
--- a/arch/arm/kernel/cacheinfo.c
+++ b/arch/arm/kernel/cacheinfo.c
@@ -23,7 +23,7 @@
 
 #define MAX_CACHE_LEVEL			7	/* Max 7 level supported */
 
-#define CTR_FORMAT_MASK	GENMASK(27, 24)
+#define CTR_FORMAT_MASK	GENMASK(31, 29)
 #define CTR_FORMAT_ARMV6 0
 #define CTR_FORMAT_ARMV7 4
 #define CTR_CWG_MASK	GENMASK(27, 24)

---
base-commit: e7bb221a638962d487231ac45a6699fb9bb8f9fa
change-id: 20250115-arm-cacheinfo-fix-9ee32f3a5e34

Best regards,
-- 
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Re: [PATCH] ARM: cacheinfo fix format field mask

[Linus Walleij]

On Wed, Jan 15, 2025 at 12:10 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:

> Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> over bits 29-31, not 24-27 of the CTR register.
>
> Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Yours,
Linus Walleij

Re: [PATCH] ARM: cacheinfo fix format field mask

[Geert Uytterhoeven]

Hi Dmitry,

Thanks for your patch!

On Wed, Jan 15, 2025 at 12:11 PM Dmitry Baryshkov
<dmitry.baryshkov@linaro.org> wrote:
> Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> over bits 29-31, not 24-27 of the CTR register.

Please add

    This causes a warning on e.g. Cortex-A8 and Cortex-A9:

        WARNING: CPU: 0 PID: 0 at arch/arm/kernel/cacheinfo.c:43
cache_line_size+0x84/0x94

so people find this patch when looking up the warning.

> Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

This fixes the warning on Cortex-A8/A9, so
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>

Note that this changes HWalign on Cortex-A9 (various Renesas SoCs,
with 1, 2, or 4 CPU cores):

    -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
    +SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1

On Cortex-A8 (BeagleBone Black, i.e. AM335x), it changes HWalign,
and causes a warning message:

    -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
    +SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
     ...
    +cacheinfo: Unable to detect cache hierarchy for CPU 0

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH] ARM: cacheinfo fix format field mask

[Russell King (Oracle)]

On Tue, Jan 21, 2025 at 03:12:13PM +0100, Geert Uytterhoeven wrote:
> Hi Dmitry,
> 
> Thanks for your patch!
> 
> On Wed, Jan 15, 2025 at 12:11 PM Dmitry Baryshkov
> <dmitry.baryshkov@linaro.org> wrote:
> > Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> > over bits 29-31, not 24-27 of the CTR register.
> 
> Please add
> 
>     This causes a warning on e.g. Cortex-A8 and Cortex-A9:
> 
>         WARNING: CPU: 0 PID: 0 at arch/arm/kernel/cacheinfo.c:43
> cache_line_size+0x84/0x94
> 
> so people find this patch when looking up the warning.
> 
> > Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> > Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> This fixes the warning on Cortex-A8/A9, so
> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Note that this changes HWalign on Cortex-A9 (various Renesas SoCs,
> with 1, 2, or 4 CPU cores):
> 
>     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
>     +SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
> 
> On Cortex-A8 (BeagleBone Black, i.e. AM335x), it changes HWalign,
> and causes a warning message:
> 
>     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>     +SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
>      ...
>     +cacheinfo: Unable to detect cache hierarchy for CPU 0
> 

Also, has this been tested on CPUs that don't implement the cache type
register?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH] ARM: cacheinfo fix format field mask

[Dmitry Baryshkov]

On Tue, 21 Jan 2025 at 16:19, Russell King (Oracle)
<linux@armlinux.org.uk> wrote:
>
> On Tue, Jan 21, 2025 at 03:12:13PM +0100, Geert Uytterhoeven wrote:
> > Hi Dmitry,
> >
> > Thanks for your patch!
> >
> > On Wed, Jan 15, 2025 at 12:11 PM Dmitry Baryshkov
> > <dmitry.baryshkov@linaro.org> wrote:
> > > Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> > > over bits 29-31, not 24-27 of the CTR register.
> >
> > Please add
> >
> >     This causes a warning on e.g. Cortex-A8 and Cortex-A9:
> >
> >         WARNING: CPU: 0 PID: 0 at arch/arm/kernel/cacheinfo.c:43
> > cache_line_size+0x84/0x94
> >
> > so people find this patch when looking up the warning.
> >
> > > Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> > > Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > > Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@samsung.com/
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > This fixes the warning on Cortex-A8/A9, so
> > Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Note that this changes HWalign on Cortex-A9 (various Renesas SoCs,
> > with 1, 2, or 4 CPU cores):
> >
> >     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
> >     +SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
> >
> > On Cortex-A8 (BeagleBone Black, i.e. AM335x), it changes HWalign,
> > and causes a warning message:
> >
> >     -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> >     +SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> >      ...
> >     +cacheinfo: Unable to detect cache hierarchy for CPU 0
> >
>
> Also, has this been tested on CPUs that don't implement the cache type
> register?

It returns -EOPNOTSUPP for anything <= v7 (or those v7-but-really-v6).
And those CPUs are required to implement the register.

>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!



-- 
With best wishes
Dmitry